Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1999-05-26
2001-04-17
Mai, Son (Department: 2818)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S041000
Reexamination Certificate
active
06218859
ABSTRACT:
BACKGROUND
1. Technical Field
The present invention relates to architecture and layout for a programmable logic device. In particular, the present invention is directed to a programmable logic device having logic cells and associated I/O pins configured in quadrants.
2. Related Art
Programmable logic devices (“PLD”s) are known in which substantial numbers of relatively elementary individual programmable logic elements, or logic cells, are provided in a two-dimensional array. Typically, the logic cells are arranged in groups. These groups may be referred to as logic array blocks (“LAB”s). The array also includes a grid of intersecting signal conductors for conducting logic signals to, from, and between the programmable logic elements and I/O pins of the PLD.
FIG. 1
shows a simplified schematic view of the architecture for a typical such PLD
10
. Details of the architecture shown in
FIG. 1
are disclosed, for example, in commonly assigned U.S. Pat. No. 5,550,782, issued Aug. 27, 1996 to Cliff et al. As shown, a PLD
10
includes a plurality of logic cells
14
a
and
14
b
; LABs
12
; and I/O pins
22
(shown schematically in blocks) along the side edges of PLD
10
. Other pins (not shown) are typically included along both the top and bottom edges of PLD
10
. Not all pins on PLD
10
are I/O pins used for data input and output. For example, some pins may used for power, grounding, and I/O control.
PLD
10
also includes a plurality of bit lines or product terms
15
, a plurality of LAB lines
16
, a plurality of global horizontal (“GH”) lines
18
, and a plurality of global vertical (“GV”) lines
20
. Product terms
15
interconnect the logic cells
14
a
,
14
b
to LAB lines
16
. LAB lines
16
interconnect all the logic cells
14
a
and
14
b
in a single LAB
12
. GH lines
18
interconnect all the LAB lines
16
in a single row of LABs
12
, and GV lines
20
interconnect all the GH lines
18
in PLD
10
. To reduce the number of interconnection lines necessary on a PLD, programmable elements are typically used to interconnect product terms
15
with LAB lines
16
, GH lines
18
with LAB lines
16
, and GV lines
20
with GH lines
18
. Such programmable elements can include, for example, RAMs, EPROMs, EEPROMS, fuses, antifuses or other device which can programmatically either connect or disconnect one line with a second intersecting line. The details and use of such programmable elements is disclosed, for example, in U.S. Pat. No. 5,550,782 to Cliff et al., which is hereby incorporated by reference in its entirety.
In PLD
10
, LABs
12
are arranged in 3 rows of 4 LABs 12 each. Each LAB
12
includes 8 logic cells
14
a
and
14
b
for performing either combinatorial or sequential logic functions. Each logic cell
14
a
,
14
b
includes at least one input and one output. I/O pins
22
are shown in 6 groups of 20 pins each. Outputs of logic cells
14
a
are directly interconnected with an I/O pin
22
and outputs of logic cells
14
b
can be interconnected with an I/O pin
22
only via a logic cell
14
a
. Logic cells
14
a
directly connected to I/O pins
22
will be referred to as direct output logic cells and logic cells
14
b
not directly connected to an I/O pin
22
will be referred to as buried logic cells. As shown in
FIG. 1
, the output of direct output logic cells
14
a
are connected both to LAB lines
16
and directly to I/O pins
22
. Each LAB
12
contains 3 direct output logic cells
14
a
and 5 buried logic cells
14
b
. I/O pins
22
can drive onto GH lines
18
and GV lines
20
. From these lines, signals can be transmitted via lab lines
16
to logic cells
14
a
and
14
b.
Through the above described interconnections of product terms
15
, LAB lines
16
, GH lines
18
, and GV line
20
, input and output signals to PLD
10
can be transmitted to or from any logic cell
14
a
,
14
b
to any other logic cell
14
a
,
14
b
or any I/O pin
22
which is used for data input and output.
However, due to the architecture of PLD
10
described above, some such signal transmissions can take longer than others. Specifically, if a signal must be transmitted through a GV line
20
prior to reaching its destination at an I/O pin
22
or logic cell
14
a
,
14
b
, the transmission time for the signal will be greater than if a signal did not have to travel over a GV line
20
. This is due to the increased total length of the transmission path over the GV line
20
and the additional programmable elements which the signal must pass through to be transmitted over a GV line
20
.
One instance in which it is necessary to transmit a signal over a GV line
20
occurs when the signal is being transmitted from one row of LABs
12
to another such row. This situation can arise when a first logic cell
14
a
,
14
b
which is the source of a signal, is driving a second logic cell
14
a
,
14
b
. If the second logic cell
14
a
,
14
b
is in a different row of LABs from the first logic cell
14
a
,
14
b
, then there will be a delay in transmission time compared with a situation in which the first logic cell
14
a
,
14
b
is in the same row as the second logic cell
14
a
,
14
b.
This additional transmission time may be undesirable in itself where high speed signal processing is required in a circuit using PLD
10
. Additionally, under some circumstances, it may not be known by a user of PLD
10
whether this additional delay will occur. This can lead to difficulty in design of appropriate circuit parameters. One such circumstance arises in connection with so called “vertical migration” of I/O pins on a PLD when additional logic cells are added to the PLD without changing the number of I/O pins.
In manufacture of PLDs of the type discussed above, it is often desirable to fabricate PLDs having different total numbers of logic cells to accommodate differing uses and price points. Additionally, in fabricating PLDs having differing numbers of logic cells, it can be relatively less expensive to use the same die or pin out pattern with the same number of I/O pins than to change the number of I/O pins. To use the same die in fabricating a PLD, and increase the total number of logic cells in the PLD, typically either additional LABs are included in each row of the device, or, to avoid rows of LABs from becoming too long, additional rows of LABs
12
are fabricated in a PLD.
Generally, the outputs of direct output logic cells
14
a
(“direct outputs”) in each row of four LABS
12
are assigned to the block of I/O pins
22
adjacent to (and above or below) that row. Additionally, the I/O pins
22
that can directly drive a row of LABs
12
(“direct inputs”) are generally assigned to the row of LABs
12
to which the I/O pins
22
are adjacent. Thus, the direct inputs in the first and third row of LABs
12
will be assigned to I/O pins (not shown) located along the top and bottom edge, respectively, of PLD
10
and to the groups of I/O pins
22
on either end of the first and third rows of LABs
12
, respectively. And, the direct outputs of the groups of I/O pins
22
at either end of the first and third rows of LABs
12
and at the top and bottom edges of PLD
10
, respectively, will be assigned to the first and third rows of LABs
12
, respectively. Similarly, the direct inputs of the second row of LABs
12
are directly connected to the two groups of I/O pins
22
on either end of the second row of LABs
12
, and the direct outputs of these two groups of I/O pins are assigned to logic cells
14
a
,
14
b
in the second row of LABs
12
.
If no additional I/O pins
22
are added to the PLD package when additional rows of LABs
12
are added to the PLD
10
, it can become necessary to “vertically migrate” the I/O pins
22
associated with the different rows of LABs
12
. That is, it can be necessary to change the direct input and direct output assignments between the groups of I/O pins
22
and rows of LABs
12
to accommodate the additional row of LABs
12
. For example, if a forth row of LABs were added to PLD
10
, then a portion of the direct input and direct output assignments
Altera Corporation
Mai Son
Morrison & Foerster / LLP
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