Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-01-26
2001-07-17
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C326S039000, C326S040000, C326S041000
Reexamination Certificate
active
06263482
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to programmable logic devices. More particularly, this invention relates to shared expander logic circuitry in such logic devices with which certain product-term logic signals may be selectively inverted.
Programmable logic devices are integrated circuits that may be programmed by a user to perform various logic functions. Some programmable logic devices use product-term architectures, in which input signals that have been combined using logical AND functions (product-terms) are further combined using logical OR functions (i.e., they are summed). Devices using product-term architectures may be based on programmable logic organized in the form of logic array blocks each of which contains a number of macrocells.
A typical macrocell contains OR logic for summing the product-terms associated with that macrocell. Each macrocell has a predetermined number of normal product-term inputs. For example, each macrocell may have five normal product-term inputs. Each macrocell may also accept a number of product-terms that have been borrowed from neighboring macrocells (sometimes referred to as parallel expanders). This allows macrocells with five normal product-term inputs to implement logic functions involving more than five product-terms.
Another type of expander connection that some macrocells use is the shared expander. Shared expanders are inverted product-terms that may be fed back to the inputs of the macrocells. Macrocells with shared expander logic can perform certain logic functions using fewer product-terms than would otherwise be possible. However, there is a speed penalty associated with conventional shared expander logic circuits, because a delay is incurred when the shared expander signals are fed back as inputs to the macrocells.
It is therefore an object of the present invention to provide arrangements that allow macrocells to handle more product-terms without needing to feed back signals to the inputs of the macrocells and without needing to borrow product-terms from neighboring macrocells.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished in accordance with the principles of the present invention by providing programmable logic device macrocells with selective inversion circuitry. The selective inversion circuitry allows product-term signals to be inverted when needed to perform a DeMorgan's transformation on a group of product terms. This approach permits logic functions that would otherwise require more product-terms than can be handled by a single macrocell to be implemented using a single macrocell. The use of conventional shared expander logic, which imposes a speed penalty for product-term inversion, is avoided.
The selective inversion macrocell circuitry of the present invention may be used with any programmable logic device having macrocells and a product-term architecture. A product-term architecture is one in which logic signals that are provided to an array or other such switching network are combined using a logical product (AND) function. The resulting product-terms are supplied to the inputs of various macrocells. Macrocells contain OR logic for logically summing the product-terms. Macrocells also typically include register logic for registering macrocell output signals. Macrocells may contain other suitable macrocell circuitry and may be arranged in logic array blocks if desired. The programmable logic devices of the present invention may be used as part of larger systems.
Further features of the invention and its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
REFERENCES:
patent: 4871930 (1989-10-01), Wong et al.
patent: 4903223 (1990-02-01), Norman et al.
patent: 4969107 (1990-11-01), Kaplinsky
patent: 5309046 (1994-05-01), Steele
patent: 5350954 (1994-09-01), Patel et al.
patent: 5757207 (1998-05-01), Lytle et al.
patent: 5764078 (1998-06-01), Agrawal et al.
patent: 6034540 (2000-03-01), Mendel
patent: 6049223 (2000-04-01), Lytle et al.
patent: 6134166 (2000-10-01), Lytle et al.
patent: 6184710 (2001-02-01), Mendel
Tirumalai et al, “Minimization Algorithms for Multiple-Valued Programmable Logic Arrays,” IEEE, Feb. 1991, pp. 167-177.*
Kozlowski et al, “An Enhanced Algorithm for the Minization of Exclusive-or Sum-of-Products for Incompletely Specified Functions,” IEEE, 1995, pp. 244-249.*
“Hybrid FPGA Architecture,” by Alireza Kaviani et al., FPGA '96, Monterey, California (1996).
“Altera 1996 Data Book,” pp. 157-179, 191-215; and 311-322, Altera Corporation, San Jose, California (1996).
Altera Corporation
Fish & Neave
Jackson Robert R.
Siek Vuthe
Smith Matthew
LandOfFree
Programmable logic device having macrocells with selectable... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Programmable logic device having macrocells with selectable..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable logic device having macrocells with selectable... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2492222