Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1998-06-26
2001-02-06
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000
Reexamination Certificate
active
06184709
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a structure and method of implementing a memory array in a programmable logic device.
DESCRIPTION OF THE PRIOR ART
Programmable logic devices (PLDs) typically include an array of configurable logic blocks (CLBs). Each CLB includes logic which is programmed to perform a particular function or functions desired by the user of the PLD. In particular PLDs, such as Xilinx's XC4000™ family of devices, writable RAM-based look-up tables are included in each CLB. The writable RAM-based look-up tables can be used to create a “user-RAM” array. However, such user-RAM arrays are inefficient because creation of the RAM array detracts from the amount of logic available to perform other operations within the PLD. That is, when a CLB is used to create user-RAM array, the logic capacity of the CLB is lost.
Moreover, the RAM arrays which can be conveniently created using the writable RAM-based look-up tables are relatively small (e.g., capable of storing only 16 to 32 bytes). To expand a RAM array (e.g., to more than 16 or 32 bytes), function generators of additional CLBs are required to perform a multiplexing function between the several smaller RAM arrays. As a result, the complexity of the signal routing for the RAM array increases, the amount of logic required by the RAM array increases, and the speed of the RAM array decreases.
For example, when implementing a 256-byte RAM, the CLB area consumed is roughly equivalent to the area of a conventional PLD. While a 256-byte RAM may seem like a large memory to implement using a PLD, such a RAM is still relatively small.
Moreover, the layout area required to make each RAM-based look-up table writable is not an insignificant percentage of the layout area of each CLB. This area penalty is incurred by each CLB, irrespective of whether it is used to create a user-RAM array. The total area penalty for a PLD depends on the size of the PLD and can be equal to the area of 100 or more CLBS.
Accordingly, it would be desirable to have a PLD which implements a user-RAM array and overcomes the problems previously discussed.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, a PLD (such as an FPGA) includes a dedicated composable RAM array having a plurality of memory tiles. The dedicated memory tiles have a relatively high density when compared with the density of writable RAM-based look-up tables typically present in CLBS. The PLD also includes an array of CLBS, wherein each of the CLBs in the array is coupled to a corresponding one of the memory tiles. The composable RAM array is accessed through the CLBs. That is, the input signals required by the memory tiles are routed through the corresponding CLBS. Similarly, the output signals provided by the memory tiles are routed out through the corresponding CLBs.
Each CLB can be configured to operate as a conventional CLB (i.e., ignore its corresponding memory tile). Alternatively, each CLB can be configured to provide an interface to its corresponding memory tile. To help achieve this, each CLB comprises a set of multiplexers for selectively routing data output signals provided by the corresponding memory tile or output signals provided by the CLB.
In addition, each memory tile is capable of being selectively coupled to one or more adjacent memory tiles, thereby allowing the size of the composable RAM array to be selected by the circuit designer. This capability also allows the composable RAM array to be configured to form a plurality of separate and independent memories.
The present invention will be more fully understood in light of the following detailed description taken together with the drawings.
REFERENCES:
patent: 4825414 (1989-04-01), Kawata
patent: 5042004 (1991-08-01), Agrawal et al.
patent: 5343406 (1994-08-01), Freeman et al.
patent: 5414377 (1995-05-01), Freidin
patent: 5583450 (1996-12-01), Trimberger et al.
“XC4000™ Series Advanced Product Information Data Sheet”, dated Feb. 2, 1996 available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Bever Hoffman & Harms LLP
Cartier Lois D.
Cho James H
Hoffman E. Eric
Tokar Michael
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