Programmable logic device architectures and methods for...

Details Programmable logic device architectures and methods for... Programmable logic device architectures and methods for...

2006-02-16

2009-11-17

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S039000

Reexamination Certificate

active

07619443

ABSTRACT:
A programmable logic device (“PLD”) architecture includes logic elements (“LEs”) grouped together in clusters called logic array blocks (LABs”). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LAB) are reduced or eliminated as compared to in the prior art. Because all (or at least more) of any LE-output-to-LE-input connections of LEs that are working together in a LAB must be routed through the general-purpose input routing resources of the LAB, it is important to conserve those resources. This is accomplished, for example, by giving greater importance to finding logic functions that have common inputs when deciding what logic functions to implement together in a LAB.

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V. Betz et al.,Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, Boston, 1999, pp. 37-50.

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