Programmable logic device and programming method

Details Programmable logic device and programming method Programmable logic device and programming method

2002-05-23

2004-04-06

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000

Reexamination Certificate

active

06717435

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a programmable logic device (PLD) and a programming method thereof
BACKGROUND ART
Today, PLDs of which the circuit configuration can be programmed at will are widely used. Program data is stored in a memory area within the PLD or external memory. The program data is transferred to an internal logic circuit to provide function settings of the PLD when the PLD is powered up or reset.
An example of the PLD is described in U.S. Pat. No. 4,870,302 in which configuration of its internal logic circuits (including wiring) can be programmed at will.
The first state of a prior-art PLD is the initial state during power-up, the second state is a program data transfer state, and the third state is a steady state. The states of the external pins and internal circuit of the PLD are unstable until the second state (transfer state) is finished. The states of the external pins and internal logic circuit do not become stable until the PLD enters a steady state after all program data is transferred to it.
The larger the size of the PLD circuit, the longer the period of the second state (transfer state) and therefore the longer a period during which the states of the external pins and internal logic circuit are unstable. In the prior art, the unstable state propagates to logic circuits adjacent to the PLD, decreasing the stability of the entire system. Especially in a configuration in which the PLD is connected to a bus within an electronic circuit system such as a personal computer, the entire system can be initialized only after the state of the PLD becomes stable during the startup of the system. Therefore it is difficult to connect the PLD to the bus in the system that has an existing, predefined startup sequence.
To avoid the above-described unstable state, a transceiver may be provided between the PLD and a logic circuit to prohibit the propagation of the unstable state. However, this approach has problems that connection delay time increases as the number of components increases, and the logic circuit cannot reference the state of the PLD until the state of the PLD becomes stable.
DISCLOSURE OF THE INVENTION
The present invention has been made in the light of the above-described problems and it is an object of the present invention to reduce the period of time in which the state of a PLD is unstable after system startup.
To solve the problems, according to the present invention, program data is divided into a pin setting data block for defining an initial state of each of a plurality of external pins and a logic setting data block for defining functions of internal logic circuits, and a PLD receives the pin setting data block before the logic setting data block. This allows the states of the external pins to become stable earlier during system startup.
According to the present invention, the PLD receives a minimum logic setting data block for defining functions (functions required for a stable operation of the system) of some of its internal logic circuits required for system startup before receiving a full logic setting data block for defining functions of all of its internal logic circuits. This allows logic circuits adjacent to the PLD to reference the state of the PLD earlier during system startup.


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