Programmable logic device and method of controlling clock...

Details Programmable logic device and method of controlling clock... Programmable logic device and method of controlling clock...

2002-03-28

2004-03-09

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000, C327S293000

Reexamination Certificate

active

06703859

ABSTRACT:

BACKGROUND OF THE INVENTION
1)
Field of the Invention
The present invention relates to a programmable logic device suitable for use as a logic device such as an FPGA (Field Programmable Gate Array), a CPLD (Complex programmable Logic Device) in which the function thereof can be changed in accordance with a program. The present invention also relates to a method of controlling a clock signal supplied to the programmable logic device.
2)
Description of the Related Art
A programmable logic device represented by a device such as an FPGA or CPLD is a logic device of which operation can be changed in accordance with a program. The programmable logic device has an advantageous nature that makes it possible to handle various kind of problems such as specification change of the product which will be brought about at an early stage of product development. For this reason, recently, technology of the logic device is rapidly developed.
Since the logic device tends to suffer from restriction when a desired circuit scale is realized or when operation speed thereof is to be increase, the programmable logic device is frequently utilized as a trial manufacture of an LSI (Large Scale Integration) at a stage of experiment and development. However owing to the recent development of device technology, allowable circuit scale is enlarged and the operation speed is increased, with the result that the logic device becomes more and more utilized practically. In particular, the logic device is frequently utilized in a part of system serving as an interface with an external system where it is difficult to construct the part of system with a microprocessor unit or a digital signal processor.
However, when the logic device is applied to a system such as a mobile communication terminal or a portable telephone, a rate of power consumption is a decisive factor, in addition to the operation speed and the circuit scale, upon selecting a device. When a programmable logic device is designed in a conventional manner, since the circuit size or the operation speed is regarded as a priority factor, the rate of power consumption has not reached a satisfactory level as compared with an LSI designed for a specific use.
In general, when the device of the rate of power consumption is large, the generated heat amount also is increased. This heat amount will influence upon the circuit operation of the device. For example, if a system employing the device is one provided outdoors which can be supplied with electric power from a power supply, the problem of power consumption reduction will not be a serious problem for such a system as compared with the above-described system such as a mobile communication terminal. However, if the device is employed in the system such as a mobile communication terminal, to suppress the heat generation due to the electric power consumption becomes a more important factor.
That is, if a circuit device having a high heat generating nature is employed in a system, a cooling device is requested for guaranteeing the operation of the circuit, which leads to a cost increase in the system. Thus, when a programmable logic device is applied to the above-described system, in order to guarantee a proper circuit operation, it is requested to employ a circuit device having a properly suppressed heat generating nature in the system upon designing the system.
FIG. 8
is a circuit diagram showing a part of an FPGA as an example of a conventional programmable logic device. As shown in
FIG. 8
, an FPGA
100
is arranged to include a plurality (there are shown 16 blocks in
FIG. 8
) of logic blocks (CLB:Configuration Logic Block)
101
arrayed in a matrix fashion,lines
102
extended to form a grid, line-changing switches
103
provided at respective intersecting points of the lines
102
extended to form a grid, and a clock net
104
for delivering a clock signal to the logic blocks
101
.
The wiring
102
connect each of the logic blocks
101
one another. The line-changing switch
103
is a unit for changing the connection relation through the lines
102
by programming. The connection relation among the logic blocks
101
can be changed by the switching of the line-changing switch
103
. Thus, a function implemented by the circuit can be changed in accordance with the program. The clock net
104
is provided independently of the lines
102
which connect the logic blocks
101
one another. In other words, the clock net
104
is ordinarily not connected to the lines
102
.
Meanwhile, the logic block
101
is made up with integrated circuit elements such as flip-flops constituting a sequential circuit and AND gates, OR gates and so on for realizing logic operation. In particular, if the flip-flop function within the logic block
101
is constructed by a CMOS (Complementary Metal Oxide Semiconductor), electric power consumed by the flip-flop circuit portion will be increased. Therefore, if the electric power consumed at the flip-flop circuit portion can be successfully suppressed, then electric power consumption in the whole FPGA can be remarkably reduced.
If an enable terminal is provided at the flip-flop circuit portion within the above-described logic block
101
, a signal can be supplied to the enable terminal so that the flip-flop operation can be controlled in switching between the enable mode and the disable mode in synchronism with the clock signal. However, the clock signal itself is inevitably delivered to the flip-flop circuit portion even if the flip-flop circuit portion is brought into the disable mode. Therefore, the electric power will be uselessly consumed at the flip-flop circuit portion due to the clock signal which is inevitably supplied to the flip-flop circuit portion during the disable mode.
For this reason, if electric power consumption is suppressed in the programmable logic device such as the FPGA described with reference to
FIG. 8
, it is desirable for the signal to be prevented from being delivered in the logic block
101
at the flip-flop circuit portion thereof when the flip-flop circuit portion is brought into the disable mode. Further, in order to prevent the clock signal from being delivered in the logic block
101
at the flip-flop circuit portion thereof when the flip-flop circuit portion is brought into the disable mode, the following two circuit arrangement strategies can be employed.
{circle around (1)} First strategy: the flip-flop circuit portion thereof is replaced with a flip-flop element having no enable terminal in the logic block
101
shown in FIG.
8
. Further, the logic block
101
is provided with a gate so that a clock signal input to the flip-flop element can be controlled in accordance with an enable signal.
{circle around (2)} Second strategy: the function as the clock net
104
is assembled together with the lines
102
so that lines as the clock net can be changed in accordance with the desired type of the logic device. In this way, halting of clock signal supply can be controlled in a manner similar to that of the other logic device components. In more concretely, the clock signal supply itself through the lines
102
can be stopped by using the ordinary logic block
101
.
However, if the logic device employs the above-introduced two strategies for preventing the clock signal from being supplied to the logic block
101
at the flip-flop circuit portion thereof upon the disable mode, the logic device will encounter the following difficulties.
Initially, in the first strategies identified by reference {circle around (1)}, although the electric power consumption brought about in the flip-flop circuit portion can be decreased, it will be difficult to arrange the wiring for supplying the clock signal to each of the logic blocks, which fact can lead to a clock skew. Thus, another buffer shall be inserted into the clock net for adjusting the clock skew. However, this buffer element will also consume electric power. To decrease the power consumption at the buffer element is additional task from the circuit design standpoint. Therefore, it is difficult to decre

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