Programmable logic device

Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...

Reexamination Certificate

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C326S040000, C326S041000

Reexamination Certificate

active

07486109

ABSTRACT:
The PLD that can change the number of input lines and the number of rail between the memories for logic according to the objective logic function, and to which the optimum design can be done to make the size of memory minimum. The memories for logic (4) are arranged in series, and LUT is memorized in them. The input variables are input from the external input lines to each memories for logic (4). The interconnection circuit (5) connects the output lines or the external input lines of memory for logic (4) in the preceding stage and the input lines of memory for logic (4) of the succeeding stage between two memories for logic (4), according to the information for connection memorized in memory for interconnections (6). By rewriting the information for connection according to the objective logic function, the interconnection circuit can be reconfigured, and the number of input lines and the number of rail can be changed. The size of memory can be suppressed to the minimum by optimizing the ratio of the number of rail and the number of input lines according to the logic function.

REFERENCES:
patent: RE34363 (1993-08-01), Freeman
patent: 2008/0100337 (2008-05-01), Kajigaya
Tsutomu Sasao et al., “Tashutsuryoku Kansu no Cascade Jutsugen to Saikosei Kano Hardware ni yoru Jitsugen”, The institute of Electronics, Information and Communication Engineers Gijutsu Kenkyu Hokoku, vol. 101, No. 3, Apr. 6, 2001, pp. 57-64; Cited in the international search report.
Akihiko Tomita et al., “LUT Array-gata PLD no Sekkei to Shisaku”, The Institute of Electronics, Information and Communication Engineers Gijutsu Kenkyu Hokoku, vol. 100, No. 475, Nov. 23, 2000, pp. 173-178; Cited in the international search report.
T. Sasao et al., “A Cascade Realization of Multiple-Output Function and Its Application to Reconfigurable Hardware,” The Institute of Electronics, Information and Communication Engineers, vol. 101, No. 3, Mile University, FTS2001-8, Apr. 2001, pp. 57-64. English abstract is included. Discussed in the specification.
T. Sasao et al. “A Cascade Realization of Multiple-Output Function for Reconfigurable Hardware” International Workshop on Logic and Synthesis (IWLS01), Lake Tahoe, CA, Jun. 12-15, 2001, pp. 225-230 w/cover page and the TOC, Discussed in the specification.
T. Tomita et al., “A Design of LUT-Array-Based PLD,” The Institute of Electronics, Information and Communication Engineers, vol. 100, No. 475, Nov. 2000, pp. 173-178. English abstract is included.
Y. Iguchi et al., “Realization of Multiple-Output Functions by Reconfigurable Cascades,” International Conference on Computer Design :VLSI in Computers & Processors (ICCD-2001), Austin, TX, Sep. 23-26, 2001. pp. 388-393 (published page number).
A. Mishchenko et al., “Encoding of Boolean Functions and Its Application to LUT Cascade Synthesis,” International Workshop on Logic and Synthesis (IWLS2002), New Orleans, Louisiana, Jun. 4-7, 2002, pp. 115-120.
T. Sasao, “Design Methods for Multi-Rail Cascades,” International Workshop on Boolean Problems (IWBP2002), Freiberg, Germany, Sep. 19-20, 2002, pp. 123-132.
T. Sasao et al., “A Design Method for Irredundant Cascades,” International Symposium on New Paradigm VLSI Computing, Sendai, Japan, Dec. 12-14, 2002, pp. 37-40.
A. Mishchenko et al., “Logic Synthesis of LUT Cascades with Limited Rails,” The Institute of Electronics, Information and Communication Engineers, Lake Biwa, VLD2002-99, Nov. 2002, pp. 1-6.
H. Gouji et al., “On a Method to Reduce the Number of LUTs in LUT cascades,” The Institute of Electronics, Information and Communication Engineers, Kitakyushu, VLD2001-99, Nov. 2001, 6 sheets, English abstract is included.
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