Programmable logic device

Details Programmable logic device Programmable logic device

1985-03-04

1988-08-02

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Testing

371 25, 364716, H03K 19177, G06F 1126

Patent

active

047617683

ABSTRACT:
An improved programmable logic device (PLD) is disclosed which employs electrically erasable memory cells which can be programmed and erased at high speed. The PLD memory cells comprise floating gate transistors as the storage elements, which are programmed and erased by Fowler-Nordheim tunneling. The PLD includes a serial register latch (SRL) which is coupled to the product terms of the PLD array. Input programming data for a selected row of the array is serially entered into the SRL, and during a programming cycle the SRL data is employed to simultaneously program the storage elements of the selected row to either the enhancement mode or the depletion mode. The data programmed into the array may be verified at high speed. The status of each of the cells in the selected row can be sensed using the normal sense amplifiers and loaded into the SRL in parallel, and thereafter serially shifted out of the PLD for external verification. The PLD output logic and sense amplifiers can be functionally validated independent of the data in the array. Test data such as apparent array patterns are serially loaded into the SRL, and thereafter forced onto the normal sense amplifier inputs, propagated through the output logic and read out of the device output pin.

REFERENCES:
patent: 3191151 (1965-06-01), Price
patent: 3566153 (1971-02-01), Spencer
patent: 3774171 (1973-11-01), Regitz
patent: 3803587 (1974-04-01), Mead
patent: 3816725 (1974-06-01), Greer
patent: 3818252 (1974-06-01), Chiba et al.
patent: 3818452 (1974-06-01), Greer
patent: 3849638 (1974-11-01), Greer
patent: 3906255 (1975-09-01), Mensch, Jr.
patent: 3912947 (1975-10-01), Buchanan
patent: 3924243 (1975-12-01), Vermuelen
patent: 3936812 (1976-02-01), Cox et al.
patent: 3949370 (1976-04-01), Reyling, Jr. et al.
patent: 3974366 (1976-08-01), Hebenstreit
patent: 4037089 (1977-07-01), Horninger
patent: 4041459 (1977-08-01), Horninger
patent: 4084152 (1978-04-01), Long et al.
patent: 4091359 (1978-05-01), Rossler
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4177452 (1979-12-01), Balasubramanian et al.
patent: 4233526 (1980-11-01), Kurogi et al.
patent: 4314360 (1982-02-01), Higuchi et al.
patent: 4321695 (1982-03-01), Redwine et al.
patent: 4414665 (1983-11-01), Kimura et al.
patent: 4434478 (1984-02-01), Cook et al.
patent: 4441074 (1984-04-01), Bockett-Pugh et al.
patent: 4476560 (1984-10-01), Miller et al.
patent: 4488267 (1984-12-01), Harrison
patent: 4490812 (1984-12-01), Guterman
patent: 4503387 (1985-03-01), Rutledge et al.
patent: 4521852 (1985-06-01), Guttag
patent: 4521853 (1985-06-01), Guttag
patent: 4543646 (1985-09-01), Ambrosius, III et al.
patent: 4583196 (1986-04-01), Koo
patent: 4590552 (1986-05-01), Guttag et al.
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4625311 (1986-11-01), Fitzpatrick et al.
patent: 4638189 (1987-01-01), Geannopoulos et al.
A. Scheibe et al., "A Two-Transistor SIMOS EAROM Cell", IEEE Journal of Solid-State Circuits, vol. SC-15, No. 3, Jun. 1980, pp. 353-357.
"An Introduction to Array Logic," H. Fleisher, L. I. Maissel, IBM Journal of Research and Development, Mar. 1975, pp. 98 et seq.
"Array Logic Macros," J. W. Jones, IBM Journal of Research and Development, Mar. 1975, pp. 120 et seq.
"PLAs Replace ROMs for Logic Designs," Electronic Designs 22, Oct. 15, 1973.
"A High Speed ESFI SOS Programmable Logic Array with an MNOS Version," IEEE Journal of Solid State Circuits, vol. SC-10, No. 5, Oct. 1975, pp. 331-336.
IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5, Oct. 1981, pp. 570-577, New York, U.S.; R. A. Wood et al.: "An Electrically Alterable PLA for Fast Turnaround-Time VLSI Development Hardware".
Electronics, vol. 53, No. 5, Feb. 1980, pp. 113-117, New York, U.S.; W. S. Johnson et al.: "16-K EE-PROM Relies on Tunneling for Byte-Erasable Program Storage".
IEEE Journal of Solid-State Circuits, vol. SC-19, No. 6, Dec. 1984, pp. 1041-1043, New York, U.S.; E. Fong et al.: "An Electrically Reconfigurable Programmable Logic Array Using A CMOS/DMOS Technology".
IEEE International Solid-State Circuits Conference, vol. 28, 32nd Conference, Feb. 1985, pp. 130-131, 322-323, Coral Gables, Florida, U.S., R. Leung et al., "A 50ns 48-Term Erasable Programmable Logic Array".
IEEE Journal of Solid-State Circuits, vol. SD-10, No. 5, Oct. 1975, pp. 331-336, New York, U.S.; K. Horninger, "A High-Speed ESFI SOS Programmable Logic Array with an MNOS Version".
ONDE Electrique, vol. 63, No. 4, Apr. 1983, pp. 33-41, Paris, FR; P. Roux et al.; "Les Memoires Non Volatiles Electriquement Reprogrammables, Bilan et Perspectives".
"Programmable Logic Array Decoding Technique," F. E. Howley, J. W. Jones, IBM Technical Disclosure Bulletin, vol. 17, No. 10, Mar. 1975.
"Field-PLAs Simplify Logic Designs," Electronic Design, Sep. 1, 1975.
"Programmable Logic Array," MOS/LSI Design and Application, W. Carr et al., pp. 255 et seq.
"Altera EP 300 Erasable Programmable Logic Device," by Altera Corporation, Santa Clara, CA, 95051, Copyright.COPYRGT. 1984, pp. 1-12.
"Automatic Page Write * * * Data Poling," vol. 1, No. 2, Jul. 23, 1983, by Reggie Huff.
Monolithic Memories Advance Information Data Sheet for "PAL64R32 HAL64R32 High Density Programmable Array Logic Devices".
Data Sheet entitled, "Product Specification Am27256 32,768.times.8-Bit Erasable PROM Advanced Micro Devices", Jul. 1983, pp. 1-6.
Pp. 3-4, 3-10 and 3-19-3-22 Monolithic Memories, Inc., Product Data Book "20-Pin PAL/HAL".
Characteristics and Operation of MOS Field Effect Devices, Richman, McGraw-Hill, Inc., 1967, pp. 114-118.

Affiliated with

Also associated with

Rating

Programmable logic device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable logic device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable logic device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-714962