Programmable logic device

Details Programmable logic device Programmable logic device

1998-04-27

2000-08-15

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 37, 326 38, 326 39, 326 40, 326 41, 326 47, G06F 738, H01L 2500

Patent

active

061042072

ABSTRACT:
An improved programmable logic device is disclosed. In one embodiment, the programmable logic device includes a plurality of I/O cells and a plurality of logic block clusters. Each logic block cluster has a set of logic blocks and a cluster routing pool, which provides programmable connections among the logic blocks and the I/O cells. A global routing pool provides programmable connections among the logic block clusters and the I/O cells. Each logic block includes a programmable logic array with a plurality of outputs. A product term sharing array in the logic block has a plurality of bus lines, each of which is coupled to at least one of the outputs of the programmable logic array. The product term sharing array also includes a plurality of output lines, each of which is coupled to a plurality of programmable interconnections that each provide a connection to one of the bus lines. Each output line of the product term sharing array is coupled to the same number of programmable interconnections. The logic block also includes a register coupled to at least one of the output lines of the product term sharing array. The register has a data input terminal and a data output terminal. First and second output multiplexers each have a first input terminal coupled to the data input terminal of the register and a second input terminal coupled to the data output terminal of the register.

REFERENCES:
patent: 5350954 (1994-09-01), Patel
patent: 5414376 (1995-05-01), Hawes
patent: 5414377 (1995-05-01), Freidin
patent: 5457410 (1995-10-01), Ting
patent: 5757207 (1998-05-01), Lytle et al.
patent: 5764080 (1998-06-01), Huang et al.
Altera Corporation Data Sheet: "MAX 9000 Programmable Logic Device Family" A-DS-M9000-05.01, Issue Feb. 1998 version. 5.01.
AMD Report: "The MACH 5 Family: Fifth Generation MACH Architecture" Publication No. 20446, Issue Mar. 1996.
Xilinx Report: "XC9500 In-System Programmable CPLD Family" Version 2.1, Issue Jan. 16, 1998.

Affiliated with

Also associated with

Rating

Programmable logic device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable logic device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable logic device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2010696