Programmable logic circuit device having look up table...

Details Programmable logic circuit device having look up table... Programmable logic circuit device having look up table...

2002-06-28

2004-11-02

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S039000, C326S040000

Reexamination Certificate

active

06812737

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an architectural technology for configuring a look up table that enables implementation area to be reduced.
2. Description of the Related Art
Recently, a programmable logic circuit device has attracted much attention as a device that can realize various logic circuits which meets diverse needs of users by programming internal circuits. Such a programmable logic circuit device is known as PLD (Programmable Logic Device) or FPGA (Field Programmable Gate Array), and recently is increasingly used not only for trial fabrication of hardwares, but also for constructing a large scale circuit (for example, a microprocessor) that has various functions in itself. These programmable logic circuits comprise look up tables (LUT: Look Up Table) as major components, and reduction of circuit area of such LUTs is strongly desired.
A look up table (LUT) as a major component of a programmable logic circuit device (PLD or FPGA) is composed of memories, and is capable of implementing an arbitrary logic circuit. Basic architecture of such a FPGA has been previously disclosed, for example, in U.S. Pat. Nos. 4,706,216, and 4,870,302. Multi-context and cluster architecture of plural LUTs in FPGA has been disclosed, for example, in U.S. Pat. Nos. 5,778,439 and 5,905,385, etc. With regard to evaluation of LUT used in FPGA (for example, evaluation of functionality and area, as well as performance evaluation, and evaluation of cluster architecture), study results are found in, for example, J. Rose et al., “Architecture of Field Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency”, IEEE J. Solid State Circuits, vol. 25, no. 5, pp. 1217-1225, October 1990, J. Rose et al., “The Effect of Logic Block Architecture on FPGA Performance”, IEEE J. Solid State Circuits, vol. 27, no. 3, pp. 281-287, March 1992, and E. Ahmed et al., “The Effect of LUT and Cluster Size on Deep Sub-micron FPGA Performance and Density”, FPGA 2000, Monterey, Calif. USA, 2000.
In a programmable logic circuit device, the number of bits M of input signal for the logic circuit that can be implemented corresponds to the number of bits of the address of memory composing the LUT, and the number of bits N of output signal corresponds to the number of output bits of the memory. Thus, a logic circuit that can be implemented in one LUT is an arbitrary logic circuit of M inputs and N outputs. Such a LUT is denoted in the present specification as M-input N-output LUT.
Conventionally, in FPGA for example, the input number M and output number N are both fixed value. Any logic circuit is divided in circuit unit of M inputs and N outputs, and is implemented using plural LUTs.
Therefore, in a conventional FPGA, even if circuit division results in a circuit having input bit number less than M, one LUT needs to be assigned to this circuit, leading to unnecessary increase of implementation area (logic and routing circuitry area; circuit area).
SUMMARY OF THE INVENTION
An object of the present invention is to reduce the circuit area of a look up table (LUT) and hence of a programmable logic circuit device. Another object of the present invention is to reduce power consumption of a programmable logic circuit device.
According to the present invention, there is provided a look up table of M inputs and N outputs, comprising a plurality of LUT units; and an internal configuration control circuit controlling an internal configuration of the plurality of LUT units.
Further, according to the present invention, there is provided a programmable logic circuit device comprising a plurality of logic blocks; a plurality of routing wires connected to each of the logic blocks; a plurality of switch circuits provided at an intersection of each of the routing wires; a plurality of connection blocks provided between an I/O line of each of the logic blocks and each of the routing wires; and an I/O block performing an input/output operation with external equipment, wherein each of the logic blocks has a look up table of M inputs and N outputs, comprising a plurality of LUT units; and an internal configuration control circuit controlling an internal configuration of the plurality of LUT units.
The internal configuration control circuit may comprise a plurality of selectors selecting I/O signals of the plurality of LUT units; and a selector control circuit controlling the selectors and defining the internal configuration of the plurality of LUT units. The selector control circuit may comprise a memory, and control the plurality of selectors in accordance with data stored in the memory.
The plurality of selectors may include an input signal selector provided at an input of at least one of the LUT units to select an input signal; and an output signal selector provided at an output of the LUT units selecting an output signal, the input signal selector and the output signal selector being controlled in accordance with the data stored in the memory. The plurality of selectors may include an input signal selector provided at an input of at least one of the LUT units to select an input signal; and an output signal selector provided at an output of the LUT units selecting an output signal, the input signal selector and the output signal selector being controlled in accordance with the input signal.
The look up table of M inputs and N outputs may be a 6-input 3-output look up table. The 6-input 3-output look up table may comprise eight 3-input 1-output LUT units. The 6-input 3-output look up table may comprise four 3-input 2-output LUT units.
In addition, according to the present invention, there is also provided a method of configuring a look up table of M inputs and N outputs, comprising the steps of providing a plurality of LUT units; and selectively controlling I/O signals of the plurality of LUT units to set a predetermined mode of an internal configuration.
The I/O signals of the plurality of LUT units may be selectively controlled in accordance with data stored in the corresponding look up table. An input signal input to at least one of the LUT units and an output signal output from the LUT unit may be selectively controlled in accordance with data stored in the corresponding look up table. An input signal input to at least one of the LUT units and an output signal output from the LUT unit may be selectively controlled in accordance with a predetermined function of the input signal.


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Rose, Jonathoan, et al., “Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency”, IEEE J. Solid-State Circuits, vol. 25, No. 5, pp. 1217-1225, Oct. 1990.
Rose, Jonathan, et al., “The Effect of Logic Block Architecture on FPGA Performance”, IEEE J. Solid-State Circuits, vol. 27, No. 3., pp. 281-287, Mar. 1992.
Ahmed, Elias et al., “The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density”, FPGA 2000, Monterey, CA USA, 2000.

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