Programmable logic array structure having reduced parasitic load

Details Programmable logic array structure having reduced parasitic load Programmable logic array structure having reduced parasitic load

1997-11-12

2000-03-07

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 44, 326 49, G06F 738

Patent

active

060345438

ABSTRACT:
The present invention provides a PLA structure having logic interposed between an AND plane and an OR plane, wherein the interposed logic provides an additional set of minterms to the OR plane such that any PLA output function can be implemented with substantially fewer input signals. In this way, parasitic loading for implementation of any particular logic function is reduced.

REFERENCES:
patent: 5235221 (1993-08-01), Douglas et al.
patent: 5712578 (1998-01-01), Conley
patent: 5872462 (1999-02-01), Ditlow et al.

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