Programmable logic array structure for semiconductor nonvolatile

Details Programmable logic array structure for semiconductor nonvolatile Programmable logic array structure for semiconductor nonvolatile

1995-02-21

1996-09-24

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 39, H03K 19177, H03K 19173

Patent

active

055594492

ABSTRACT:
The PLA, which implements a state machine of a nonvolatile memory, presents a dynamic NAND-NOT-NOR configuration, and the timing signals for correct reading of the PLA are generated by a clock generator which generates a monostable succession of read enabling signals on receiving a predetermined switching edge of an external clock signal. The clock generator enables evaluation of the AND and OR planes of the PLA and subsequently storage of the results through sections duplicating the propagation delays of the signals in the corresponding parts of the PLA. Reading is terminated as soon as completion of the storage step is indicated, so that reading of the PLA lasts only as long as strictly necessary, thus preventing erroneous switching while at the same time ensuring correct reading of the PLA.

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Lin, "A 4.mu.m NMOS NAND Structure PLA," IEEE J. of Solid-State Circuits 16(2): 103-107, 1981.
Linz, "A Low-Power PLA for a Signal Processor, " IEEE J. of Solid-State Circuits 26 (2): 107-115, 1991.

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