Programmable logic array integrated circuit with general-purpose

Details Programmable logic array integrated circuit with general-purpose Programmable logic array integrated circuit with general-purpose

1995-03-22

1996-11-05

Hudspeth, David R.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 39, 36523002, H03K 19177

Patent

active

055721486

ABSTRACT:
A programmable logic device integrated circuit incorporating a memory block. The memory block (250) is a general-purpose memory configurable as a random access memory (RAM) or a first-in first-out (FIFO) memory. In one embodiment, the organization of memory block (250) may have variable word size and depth size. Memory block (250) is coupled to a programmable interconnect array (213). Signals from the programmable interconnect array (213) may be programmably coupled to the data, address, and control inputs of the memory block. Data output and status flag signals from the memory block are programmably coupled to the programmable interconnect array (213).

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Xilinx XC4000, The Programmable Logic Data Book, 1994, pp. 2-7 through 2-46.
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Bursky, D. "Combination RAM/PLD Opens New Application Options" (1991) Electronic Design, May 23, 1991, pp. 138-140.

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