Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent
1996-07-24
2000-04-11
Santamauro, Jon
Electronic digital logic circuitry
Multifunctional or programmable
Array
326 38, H03K 19177
Patent
active
060492236
ABSTRACT:
A programmable logic device integrated circuit incorporating a memory block. The memory block (250) is a general-purpose memory configurable as a random access memory (RAM) or a first-in first-out (FIFO) memory. In one embodiment, the organization of memory block (250) may have variable word size and depth size. Memory block (250) is coupled to a programmable interconnect array (213). Signals from the programmable interconnect array (213) may be programmably coupled to the data, address, and control inputs of the memory block. Data output and status flag signals from the memory block are programmably coupled to the programmable interconnect array (213).
REFERENCES:
patent: Re34363 (1993-08-01), Freeman
patent: Re34444 (1993-11-01), Kaplinsky
patent: 4293783 (1981-10-01), Patil
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4670749 (1987-06-01), Freeman
patent: 4706216 (1987-11-01), Carter
patent: 4780846 (1988-10-01), Tanabe et al.
patent: 4825414 (1989-04-01), Kawata
patent: 4831591 (1989-05-01), Imazeki et al.
patent: 4855958 (1989-08-01), Ikeda
patent: 4891788 (1990-01-01), Kreifels
patent: 4940909 (1990-07-01), Mulder et al.
patent: 4963770 (1990-10-01), Keida
patent: 4975601 (1990-12-01), Steele
patent: 5042004 (1991-08-01), Agrawal et al.
patent: 5122685 (1992-06-01), Chan et al.
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5274600 (1993-12-01), Ward et al.
patent: 5313119 (1994-05-01), Cooke et al.
patent: 5315178 (1994-05-01), Snider
patent: 5329460 (1994-07-01), Agrawal et al.
patent: 5343406 (1994-08-01), Freeman et al.
patent: 5352940 (1994-10-01), Watson
patent: 5406525 (1995-04-01), Nicholes
patent: 5408434 (1995-04-01), Stansfield
patent: 5414377 (1995-05-01), Freidin
patent: 5426378 (1995-06-01), Ong
patent: 5432719 (1995-07-01), Freeman et al.
patent: 5530378 (1996-06-01), Kucharewski, Jr. et al.
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5566123 (1996-10-01), Freidin et al.
patent: 5570040 (1996-10-01), Lytle et al.
patent: 5572148 (1996-11-01), Lytle et al.
patent: 5668771 (1997-09-01), Cliff et al.
patent: 5809281 (1998-09-01), Steele et al.
patent: 5835405 (1998-11-01), Tsui et al.
patent: B14617479 (1993-09-01), Hartmann et al.
Nelson, "Embedded Memory Enhances Programmable Logic for Complex, Compact Designs," EDN Magazine, Nov. 7, 1996, pp. 91-106.
Bursky, D. "Combination RAM/PLD Opens New Application Options" (1991) Electronic Design, May 23, 1991, pp. 138-140.
Plus Logic, "FPSL5110 Intelligent Data Buffer" Data Sheet, pp. 1-3.
Xilinx XC4000, "The Programmable Logic Data Book", 1994, pp. 2-7 through 2-46.
MAX 5000, Altera Data Book, Aug. 1993, pp. 149-160.
"Implementing FIFO Buffers in FLEX 10K Devices", Altera Corporation, Jan. 1996, Ver. 1, Application Note 66, pp. 1-12.
"Configuring FLEX 10K Devices", Altera Corporation, Dec. 1995, Ver. 1, Application NOte 59, pp. 1-24.
"Flex 10K Embedded Programmable Logic Family", Altera Corporation, Jul. 1995, Ver. 1, Data Sheet, pp. 1-56.
"Implementing RAM Functions in FLEX 10K Devices", Altera Corporation, Nov. 1995, Ver. 1, Application Note 52, pp. 1-8.
Lattice Semiconductor Corporation Product News Release, Mar. 4, 1996.
Lattice Semiconductor Corporation Data Sheet, Jan., 1996.
Bursky, D. "CPLDs Add Dedicated Memory, Counters To Up Performance,", Mar. 4, 1996.
Masumoto, Rodney T., "Configurable On-Chip RAM Incorporated into High Speed Logic Array," IEEE Custom Integrated Circuits Conference, Jun. 1985, CH2157-6/85/0000-0240, pp. 240-243.
Landry, Steve, "Application--Specific ICs, Relying on RAM, Implement Almost Any Logic Function," Electronic Design, Oct. 31, 1985, pp. 123-130.
Bursky, Dave, "Shrink Systems with One-Chip Decoder, EPROM, and RAM," Electronic Design, Jul. 28, 1988, pp. 91-94.
Kawana, Keiichi et al., "An Efficient Logic Block Interconnect Architecture for User-Reprogrammable Gate Array," IEEE 1990 Custom Integrated Circuits Conference, May 1990, CH2860-5/90/0000-0164, pp. 31.3.1-4.
Plus Logic "FPSL5110 Intelligent Data Buffer" Product Brief, Plus Logic, Inc., San Jose, California, Oct. 1990, pp. 1-6.
Shubat, Alexander et al., "A Family of User-Programmable Peripherals with a Functional Unit Architecture," IEEE Jor. of Solid-State Circuits, vol. 27, No. 4, Apr. 1992, 0018-9200/92$03.00, pp. 515-529.
"AT&T's Orthogonal ORCA Targets the FPGA Future," 8029 Electronic Engineering, 64, No. 786, Jun. 1992, Woolwich, London, GB, pp. 9-10.
Bursky, Dave, "FPGA Advances Cut Delays, Add Flexibility," 2328 Electronic Design, 40, No. 20, Oct. 1, 1992, Cleveland, OH, pp. 35-43.
Smith, Daniel, "Intel's FLEXlogic FPGA Architecture," IEEE 1063-6390/93, Wilson [29], 1993 pp. 378-384.
Bursky, Dave, "Denser, Faster FPGAs Vie for Gate-Array Applications," 2328 Electronic Design, 41, No. 11, May 27, 1993, Cleveland, OH, pp. 55-75.
Ngai, Kai-Kit Tony, "An SRAM-Programmable Field-Reconfigurable Memory," UMI Dissertation Services, Jun. 1994, University of Toronto, pp. i-68.
Kautz, "Cellular Logic in Memory Arrays," IEEE Trans. on Computers, vol. C-18, No. 8, Aug. 1969, pp. 719-727.
Stone, "A Logic in Memory Computer," IEEE Trans. on Computers, Jan. 1970, pp. 73-78.
Manning, "An Approach to Highly Integrated Computer Maintained Cellular Arrays," IEEE Trans. on Computers, vol. C-26, No. 6, Jun. 1977, pp. 536-552.
Patil et al., "A Programmable Logic Approach for VLSI," IEEE Trans. on Computers, vol. C-28, No. 9, Sep. 1979, pp. 594-601.
Seitz, "Concurrent VLSI Architectures," IEEE Trans. on Computers, vol. C-33, No. 12, Dec. 1984, pp. 1247-1265.
Hsieh et al., "Third Generation Architecture Boosts Speed and Density of Field Programmable Gate Arrays," Proc. of IEEE CICC Conf., May 1990, pp. 31.2.1 to 31.2.7.
Ling et al., "WASMII: A Data Driven Computer on a Virtual Hardware," Proc. of IEEE Field Prog. Custom Computing Machines Conf., Napa, California, Apr. 1993, pp. 33-42.
Casselman, "Virtual Computing and The Virtual Computer," IEEE, Jul. 1993, p. 43.
Quenot et al., "A Reconfigurable Compute Engine for Real-Time Vision Automata Prototyping," Proc. of IEEE FCCM Conf., Napa, California, Feb. 1994, pp. 91-100.
Larrson, T, "Programmable Logic Circuits: The Luxury Alternatives are Coming Soon," Elteknik-med-Aktuell Electronik, No. 4, Feb. 25-Mar. 9, 1988, pp. 37-8, (with English abstract).
Intel Preliminary Datasheet, "iFX780: 10ns FLEXlogic FPGA with SRAM Option," Nov. 1993, pp. 2-24 to 2-46.
Quinnell, Richard A., "FPGA Family Offers Speeds, Density, On-Chip RAM, and Wide-Decode Logic," EDN Dec. 6, 1990, pp. 62-63.
Satoh, Hisayasu et al., "A 209K-Transistor ECL Gate Array with RAM," IEEE Jor. of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1275-1279.
Faria Donald F.
Lytle Craig S.
Altera Corporation
Santamauro Jon
LandOfFree
Programmable logic array integrated circuit with general-purpose does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Programmable logic array integrated circuit with general-purpose, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable logic array integrated circuit with general-purpose will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1179580