Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1998-12-09
2001-03-20
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C326S093000
Reexamination Certificate
active
06204688
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to programmable logic array integrated circuit devices, and more particularly to the interconnection resources that are provided in such devices.
Cliff et al. U.S. patent application Ser. No. 08/442,795, filed May 17, 1995, shows programmable logic array integrated circuit devices of great power and flexibility. (The Cliff et al. '795 application is hereby incorporated by reference herein.) There are many situations in which the full power and flexibility of these devices are needed. There are other situations, however, in which it would be desirable to economize somewhat on these devices. Research therefore continues into ways to provide nearly the capability of the above-mentioned devices, but to do so more efficiently.
The interconnection resources in programmable logic devices are extremely important to the full usability of the logic on those devices. However, these interconnection resources consume a substantial fraction of the total resources of the device. More efficient interconnection resources can therefore contribute greatly to reducing the size and therefore the cost of programmable logic devices.
In view of the foregoing, it is an object of this invention to provide improved programmable logic array integrated circuit devices.
It is a more particular object of this invention to provide more efficient and economical interconnection resources for programmable logic array integrated circuit devices.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic array integrated circuit devices having a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. (Each such row or column may be considered a linear array.) Each region has a plurality of inputs and is programmable to provide one or more outputs which are one or more logical functions of the inputs. For example, each region may include one or more logic modules, each of which has several inputs and is programmable to produce an output which is any of several logical functions of the inputs.
A plurality of “horizontal” inter-region interconnection conductors is associated with each row of regions for conveying signals along that row. A plurality of “vertical” inter-region interconnection conductors is associated with each column of regions for conveying signals along that column. A plurality of local conductors is associated with each of the regions for conveying signals into or out of the region and for conveying signals between various parts (e.g., logic modules) of the region. The local conductors associated with each region are programmably connectable to the inputs and outputs of that region. The local conductors associated with each region are also programmably connectable to the horizontal and vertical conductors adjacent to that region.
At least some of the local conductors associated with each region are preferably provided as two programmably connectable segments. A first of these segments includes programmable connections to adjacent horizontal and vertical conductors. The second segment includes programmable connections to inputs and at least one output of the associated region. Thus the first segment can be used by itself to connect horizontal and vertical conductors, while the second segment is being used for intra-region communication. Alternatively, the two segments can be connected to one another for use of the local conductor to convey a signal into or out of the region.
The association between local conductor groups and regions is preferably not one-for-one. Rather, each region is preferably disposed between two groups of local conductors, and each group of local conductors is preferably disposed between two regions. In other words, the regions and local conductors are interleaved or interdigitated. Each region can then get some of its inputs from the local conductors on each side of that region, and each region can apply its outputs to local conductors on both sides of that region. Correspondingly, each group of local conductors can convey signals to, from, or between logic regions on both sides of that group.
The features described in the two preceding paragraphs greatly enhance the usability of the local conductors. Segmenting them allows them to serve several different purposes. Interleaving them between logic regions allows them to be shared by two logic regions. Such sharing may allow the overall number of local conductors to be reduced, with no significant loss of routing flexibility. This arrangement of the local conductors between adjacent regions also allows communication between such regions without the need to employ more general interconnection resources (e.g., the above-mentioned horizontal conductors) to make these connections.
In the most preferred embodiments, the horizontal conductors associated with each row are provided in several (i.e., at least three) different lengths. Some of these conductors span all of the logic regions in the row. Horizontal conductors of a shorter second length span a second number of logic regions which is substantially less than all of the regions in the row. Horizontal conductors of a still shorter third length span a still smaller number of logic regions. For example, a row of logic regions may be subdivided by halves, quarters, and eighths, with some of the associated horizontal conductors spanning the entire row, some spanning each half of the row, some spanning each quarter of the row, and some spanning each eighth of the row. In this way, relatively short interconnections can often be made using only a relatively short interconnection conductor, thereby saving the longer conductors for longer interconnections. The principles summarized in this paragraph can alternatively or additionally be applied to the vertical conductors.
Because of the large number of regions and associated local conductors, it can be especially helpful to economize in the way in which the local conductors are programmably connectable to region inputs. In the especially preferred embodiments, the local conductor groups are subdivided into at least two main subgroups. These main subgroups are further subdivided into smaller secondary subgroups (e.g., of four local conductors each). Each of the main subgroups is traversed by the same number of intermediate conductors as there are local conductors in each secondary subgroup. Each local conductor in each secondary subgroup is programmably connectable to a respective one of the intermediate conductors that traverse that local conductor. All of these programmable connections for a given secondary subgroup are controlled in common by a common programmable element. Additional programmable elements select one of the intermediate conductors associated with each main subgroup as the one to provide an intermediate output signal for that main subgroup. Further programmably controlled selection circuitry selects two final output signals from the two intermediate output signals. These final output signals are used as logic region input signals. A structure of this kind can significantly reduce the required number of programmable control elements.
In addition to their primary inputs, which have been discussed above, the logic regions (or logic modules within logic regions) may require so-called secondary signals (e.g., for clocking registers in the regions, for clearing those registers, etc.). To reduce the amount of interconnection circuitry required to supply such secondary signals, while still maintaining considerable flexibility in the provision of those signals, each region may have associated secondary signal selection circuitry for selecting secondary signals either from dedicated secondary signal conductors that extend adjacent to each region or from normal inputs to the logic region. The normal inputs that are thus selectable to provide secondary signals may all be associated with o
Cliff Richard G.
Heile Francis B.
Huang Joseph
Mendel David W.
Pedersen Bruce B.
Altera Corporation
Fish & Neave
Jackson Robert R.
Le Don Phu
Shvarts Alexander
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