Programmable logic array integrated circuit devices

Details Programmable logic array integrated circuit devices Programmable logic array integrated circuit devices

2003-02-06

2004-11-09

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S039000

Reexamination Certificate

active

06815981

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to programmable logic array integrated circuit devices, and more particularly to improved features for such devices (e.g., improved programmable interconnectivity between the programmable logic regions of such devices).
Programmable logic array integrated circuit devices are well known, as shown, for example by Pedersen et al. U.S. Pat. No. 5,260,610 and Cliff et al. U.S. Pat. No. 5,260,611. Such devices often include a large number of regions of programmable logic disposed on the device in a two-dimensional array of intersecting “rows” and “columns” of such regions. Each region is programmable to perform any of several logic functions on signals applied to the region. Each row may have associated “horizontal” conductors for conveying signals to, from, and/or between the regions in the row. Each column may have associated “vertical” conductors for conveying signals from row to row. Programmable connections may be provided for selectively connecting the conductors adjacent to each region to the inputs and outputs of the region, and also for selectively connecting various conductors to one another (e.g., connecting a horizontal conductor to a vertical conductor). Interconnection of regions through the above-mentioned conductors and programmable connections makes it possible for the programmable logic array device to perform much more complicated logic functions than can be performed by the individual regions.
Advances in integrated circuit fabrication technology have made it possible to produce programmable logic array devices with very large numbers of logic regions. As the number of logic regions increases, however, it becomes increasingly important to select the numbers and arrangements of the interconnection conductors and the programmable connections between those conductors and the regions. Complete generality of these interconnection resources (i.e., so that any desired interconnection can be made no matter what other interconnections are made) would lead to exponential growth in the chip area occupied by those resources as the number of logic regions increases. This is especially disadvantageous in the case of reprogrammable devices because of the larger size and greater circuit loading and signal propagation delay of reprogrammable interconnection elements as compared to one-time-only programmable interconnection elements. (One-time-only programmable devices are shown, for example, El Gamal et al., “An Architecture for Electrically Configurable Gate Arrays,” IEEE Journal of Solid-State Circuits, Vol. 24, No. 2, June 1989, pp. 394-98; El-Ayat et al., “A CMOS Electrically Configurable Gate Array,” IEEE Journal of Solid-State Circuits, Vol. 24, No. 3, June 1989, pp. 752-62; and Elgamal et al. U.S. Pat. No. 4,758,745.) Moreover, most of any completely general interconnection resources would be unused and therefore wasted in virtually all applications of the device. On the other hand, many applications of the device may require substantial interconnection resources, and because the device is intended to be a general-purpose device, it is extremely important to commercial success that the device be capable of satisfying a very wide range of potential applications, many of the requirements of which cannot be known in advance by the designer of the programmable logic array device.
Considerations such as the foregoing make it essential to provide increasingly sophisticated interconnection resources in programmable logic array devices, and especially in reprogrammable logic array devices. The aim is to hold down the fraction of the “real estate” of the chip that is devoted to interconnection resources, e.g., by optimizing various features of those resources, by increasing the flexibility with which those resources can be used, etc. Moreover, this is preferably done without undue circuit loading and speed penalties due to passing signals through excessive numbers of switches or tapping conductors to large numbers of switches. (Compare the above-mentioned El Gamels, El-Ayat, and Elgamal references, as well such other references as Freeman U.S. Pat. No. Re. 34,363 and Carter U.S. Pat. No. 4,642,487, all of which rely heavily on programmably piecing together relatively short conductor segments when longer conductors are needed.)
In view of the foregoing it is an object of this invention to provide improved programmable logic array devices.
It is a more particular object of this invention to provide improved arrangements of interconnection resources on programmable logic array integrated circuits.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic array integrated circuit devices having the traditional two-dimensional array of programmable logic regions with horizontal conductors associated with each row and vertical conductors associated with each column, but with the difference that some of the horizontal conductors associated with each row extend continuously or substantially continuously along only approximately half the length of the row. Thus each row is divided into two mutually exclusive halves, with some “half-horizontal” conductors extending along each of the two halves. In this way a half-horizontal conductor can be used to make connections to, from, and/or between logic regions in a half of the row without having to use a much longer than necessary full-horizontal conductor for this purpose. The full-horizontal conductors (which extend continuously or substantially continuously along the entire length of a row, and which are sometimes also referred to as global horizontal conductors) can be saved for signals that must be transmitted beyond either half of the row. Because two end-to-end half-horizontal conductors occupy the same space as one full-horizontal conductor, the provision of half-horizontal conductors makes more efficient use of the horizontal conductor real estate on the chip. In particular, the half-horizontal conductors allow the number of full-horizontal conductors to be reduced. Reducing the number of horizontal conductors also helps reduce the size of the programmable switch arrays used to programmably connect the horizontal conductors to the inputs of each logic region. Axially aligned and adjacent half-horizontal conductors are preferably not directly connectable to one another. Thus there is preferably no possibility of programmably optionally piecing together axially aligned half-horizontal conductors to make longer horizontal conductors. Instead, that longer horizontal conductor resource is the global horizontal conductors, which are preferably continuous or substantially continuous and not made up of pieced-together shorter conductors.
Each logic region output signal is preferably programmably connectable to one full-horizontal conductor and one half-horizontal conductor. Each full- and half-horizontal conductor associated with a row is drivable by either of two outputs of logic regions in that row. Each logic region output is also programmably connectable to a vertical conductor. Having two logic region outputs share each full- and half-horizontal conductor also helps to reduce the number of horizontal conductors that must be provided. Again, this helps reduce the size of the programmable switch arrays used to programmably connect the horizontal conductors to the inputs of each logic region.
Both the half-horizontal and the full-horizontal conductors are programmably output-connectable to so-called “horizontal” input/output (“I/O”) pins for purposes of outputting signals from the chip. For purposes of inputting to the chip, both the half-horizontal and the full-horizontal conductors could be programmably input-connectable to the horizontal I/O pins, but in the preferred embodiments only the full-horizontal conductors are thus programmably input-connectable.
Certain full-horizontal conductors (e.g., those that can receive inputs from the horizontal I/O pins) are programmably connectable t

Affiliated with

Also associated with

Rating

Programmable logic array integrated circuit devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable logic array integrated circuit devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable logic array integrated circuit devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3319701