Programmable logic array having power-saving banks

Details Programmable logic array having power-saving banks Programmable logic array having power-saving banks

1996-05-29

1997-09-30

Westin, Edward

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 40, H03K 19177

Patent

active

056729847

ABSTRACT:
A programmable logic array comprises a PLA area having a plurality of banks wherein each of the bank has an array of a discharge typed logic circuit for decoding a micro-code, a command code is inputted to each bank every cycle for executing a predetermined command, and each bank outputs bank selection data for determining by which bank a command of a next cycle be decoded at the previous cycle, and a control circuit for selecting one bank for decoding the command code of the next cycle from the plurality of banks based on the bank selection data of each bank in the previous cycle, and for sending a command code to only the selected one bank to perform discharge of a discharge typed logic circuit, thereby stopping operations of other banks.

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Hennessy et al.; "Computer Architecture, A Quantitative Approach"; .COPYRGT.1990 by Morgan Kaufmann Publishers, Inc.; pp. 204-206.
Mano, M. Morris, "Computer System Architecture" 3rd Edition; .COPYRGT.1993 by Prentice-Hall, Inc.; pp. 450-453.
"PLD For State-Machine Designs Features Low-Power Operation", Computer Design, Apr., 1991, p. 117.

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