Programmable logic array having an improved testing arrangement

Details Programmable logic array having an improved testing arrangement Programmable logic array having an improved testing arrangement

1988-10-19

1990-04-24

Gossage, Glenn A.

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

365185, 365201, 36518903, 307465, 307468, 34082591, G11C 700, H03K 19173

Patent

active

049205153

ABSTRACT:
A programmable logic array (PLA) whose AC characteristics such as an input-to-output delay characteristic can be measured includes a plurality of input lines, a plurality of product term lines, a plurality of non-volatile memory elements, and a test input line to which a test signal may be applied. Those non-volatile memory elements which are connected to the input lines other than the test input line are turned OFF in a test mode, while turning all product term lines other than the product term line whose AC characteristics are to be measured, to a low level. Only those memory elements whose AC characteristics are to be measured are operable in an ON-OFF fashion and only the product term line to be measured is ready to have a low level or a high level. When a test signal is applied to the test input line, it is routed to the operable memory elements and product term line only.

REFERENCES:
patent: 4525714 (1985-06-01), Still et al.
patent: 4617649 (1986-10-01), Kyomasu et al.
patent: 4780628 (1988-10-01), Illman
Grassl, "A Self Testing PLA", IEEE ISSCC Digest of Technical Papers, Feb. 10, 1982, pp. 60-61.

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