Programmable logic array and method for its design using a three

Details Programmable logic array and method for its design using a three Programmable logic array and method for its design using a three

1997-11-26

1999-02-16

Santamauro, Jon

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 41, 326 45, 364490, H03K 19177

Patent

active

058724621

ABSTRACT:
A PLA whose slowest product terms are located as close as possible to the true/complement generators or input buffers. The associated input buffers and product terms are partitioned into two or more sections. A modified gap cell recombines the product terms before propagating the signal into an array.

REFERENCES:
patent: 4920515 (1990-04-01), Obata
patent: 4990801 (1991-02-01), Caesar et al.
patent: 5101122 (1992-03-01), Shinonara
patent: 5471155 (1995-11-01), Steele
patent: 5576636 (1996-11-01), Baucom

Affiliated with

Also associated with

Rating

Programmable logic array and method for its design using a three does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable logic array and method for its design using a three, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable logic array and method for its design using a three will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2065370