Programmable logic array

Details Programmable logic array Programmable logic array

1983-07-18

1987-04-21

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, 364716, H03K 19096, H03K 19173, H03K 1920

Patent

active

046599487

ABSTRACT:
A single plane programmable logic array (PLA) using dynamic CMOS logic has switching transistors located at specific locations within a row-column matrix. The transistors within a column are series connected and have their gates common connected in rows. PMOS and NMOS control transistors conduct exclusively to connect output and input ends of the columns respectively to logic 1 or logic 0 in successive phases of a common clock. Control inputs are applied to specific rows. By applying data inputs to column input ends and interconnecting all the column output ends, the PLA is configured to function as a multiplexer. By setting the input end of columns to logic 0 and selectively interconnecting output ends of the columns, the PLA is configured to perform other combinational logic functions.

REFERENCES:
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patent: 3829710 (1974-08-01), Hirasawa et al.
patent: 3945000 (1976-03-01), Suzuki et al.
patent: 3965369 (1976-06-01), Hatsukano
patent: 3989955 (1976-11-01), Suzuki
patent: 4069426 (1978-01-01), Hirasawa
patent: 4183093 (1980-01-01), Kawagoe
patent: 4277836 (1981-07-01), Kawakami
patent: 4404654 (1983-09-01), Kamuro et al.

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