Programmable logic architecture incorporating a content...

Details Programmable logic architecture incorporating a content... Programmable logic architecture incorporating a content...

2000-10-11

2001-12-04

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S041000, C326S039000, C326S038000

Reexamination Certificate

active

06326807

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a programmable logic device, and to a programmable logic device operable as a content addressable memory (CAM).
2. Description of the Related Art
A programmable logic device (PLD) is a programmable integrated circuit that allows the user of the circuit, using software control, to customize the logic functions the circuit will perform. The logic functions previously performed by small, medium, and large scale integration integrated circuits can instead be performed by programmable logic devices. When a typical programmable logic device is supplied by an integrated circuit manufacturer, it is not yet capable of performing any specific function. The user, in conjunction with software supplied by the manufacturer or created by the user or an affiliated source, can program the PLD to perform the specific function or functions required by the user's application. The PLD can then function in a larger system designed by the user just as though dedicated logic chips were employed. For the purpose of this description, it is to be understood that a programmable logic device refers to once programmable as well as reprogrammable devices.
Programmable logic encompasses all digital logic circuits that are configured by the end user, including PLDs, field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). These different programmable logic devices can have substantially different architectures. Once common architecture for PLDs or CPLDs is known as an embedded array programmable logic design.
The general architecture of an embedded array programmable logic design will be generally familiar to those knowledgeable of the FLEX10K™ logic family of devices manufactured by the Altera Corporation of San Jose, Calif. Such an architecture, for example, is described in U.S. Pat. No. 5,550,782 and Altera Data Book 1996, both of which are incorporated herein by reference.
Referring initially to
FIG. 1
, a CPLD
100
with an embedded array programmable logic design will be described. Although only a few logic array blocks or memory blocks are illustrated, it should be appreciated that any number may be provided in order to meet the needs of a particular system.
The CPLD
100
includes a plurality of logic array blocks (LAB)
110
and a plurality of embedded array blocks (EAB)
112
. Each EAB
112
includes a memory array
111
. Each LAB
110
includes a plurality of logic elements LE
113
which are each capable of performing simple logic functions.
As shown in
FIG. 1
, the plurality of LABs
110
and the plurality of EABs
112
are programmably interconnected by way of a plurality global horizontal conductors
114
and a plurality of global vertical conductors
116
to form a logic and memory array. The global horizontal conductors
114
couple to the horizontal ports
108
, and the global vertical conductors
116
couple to the vertical ports
106
.
The EAB is a flexible block of random access memory (RAM) with registers on the input and output ports. As is known in the art, a RAM is an array of individual memory cells, of which each cell includes a plurality of transistors configured to store digital data in the form of a single bit. Typically, the individual memory cells are arranged to form data words of varying length depending upon the particular application. In practice, data words may be of any length, however, data word lengths of 1, 8, 16, or 32 bits are common but any word length desired by the user is possible. As structured, the RAM device has the ability to access, or read, each stored data bit or data word independently of any other stored data bit or word by selectively enabling desired rows and columns.
Many applications such as database machines, image or voice recognition devices, or computer and communication networks require high speed searches of databases, lists, or patterns. Commonly, high speed searches using RAM employ search algorithms such as binary, tree-based searches, or look aside tag buffers. Unfortunately, the structure of the RAM requires these algorithms to sequentially compare the desired information against the pre-stored data within the RAM in a manner that is relatively slow, thereby leading to unacceptable search times.
To address the need for high speed searches in large databases, lists or patterns, a device known in the art as the content addressable memory (CAM) was developed. The CAM is a memory device that accelerates the applications such as database machines, image or voice recognition devices, or computer and communications networks that require fast searches of a database, list, or pattern. CAMs may have significant performance advantages over use of RAM in performing high speed searches since CAMs compare the entire list of pre-stored data simultaneously. Typically, in performing high speed searches, the CAM based search engine delivers up to an order of magnitude faster performance than a RAM based search engine.
In view of the foregoing, it would be advantageous and therefore desirable to provide a programmable logic device operable as an efficient configurable content addressable memory.
SUMMARY OF THE INVENTION
Broadly speaking, the invention relates to an integrated circuit that can be configured to operate as a content addressable memory. Typically, the integrated circuit chip is a complex programmable logic device architecture (CPLD). The complex programmable logic device can be a part of a larger system such as for example, a reconfigurable computer just as easily as a stand alone chip. By using the reprogrammable nature of the complex programmable logic device, the invention is able to be configured as needed to operate as a content addressable memory. The ability to be configured as needed to operate as a content addressable memory greatly increases the number of high speed data retrieval and communication applications to which the complex programmable logic device can be used.
In one embodiment of the invention, an integrated circuit is disclosed. The integrated circuit includes an address selector unit having an address selector input node and an address selector output node and a first synchronous data latch coupled to the address selector unit output node operable in an synchronous storage mode. The integrated circuit also includes a selector decoder unit coupled to said first synchronous data latch and a system clock coupled to said first synchronous data latch. Based upon a received request data word, the address selector unit provides an appropriate address select signal to the first synchronous data latch which, in turn, stores the appropriate address select signal in accordance with the system clock, and wherein the stored address select signal is then passed to the selector decoder unit in accordance with the system clock whereupon the selector decoder unit provides an appropriate output signal to a selector decoder unit output node.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.


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Stansfield, Anthony and Page, I

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