Programmable latches that include non-volatile programmable...

Details Programmable latches that include non-volatile programmable... Programmable latches that include non-volatile programmable...

2000-03-01

2001-07-24

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having fuse element

C365S230080, C365S189050, C365S185140, C327S525000

Reexamination Certificate

active

06266290

ABSTRACT:

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH
Not applicable.
BACKGROUND OF THE INVENTION
The present invention relates to programmable latches that include non-volatile programmable elements. Examples of non-volatile programmable elements are fuses.
Programmable latches with fuses are used in integrated circuits to enable modification of the circuits without changing the masks used for circuit fabrication. For example, fuse programmable latches are used to replace defective memory cells with spare cells in semiconductor memories.
FIG. 1
shows one such latch described in U.S. Pat. No. 4,546,455 issued Oct. 8, 1985 to Iwahashi et al. Fuse F
1
is connected between the power supply terminal VDD and the latch output terminal OUT. An NMOS transistor
110
is connected between the terminal OUT and the ground terminal. Three serially connected inverters
120
.
1
,
120
.
2
,
120
.
3
are provided between the output terminal OUT and the gate of transistor
110
.
If fuse F
1
is intact, the terminal OUT is pulled to VDD. The inverters
120
keep transistor
110
off. If fuse F
1
is blown, the terminal OUT is at the ground voltage. The inverters turn transistor
110
on to keep the terminal OUT at ground.
Bypass capacitor
130
is connected between the input of inverter
120
.
3
and the ground terminal to insure correct initialization of the latch on power-up. More particularly, when the power is off, transistor
110
is non-conductive. Therefore, terminal OUT is floating. According to U.S. Pat. No. 4,546,455, the terminal OUT may “tend to have its potential raised to a logic level ‘1’”. In addition, the terminal OUT potential may become “unstable due to the capacitive coupling” in the integrated circuit. Consequently, during operation, transistor
110
could be off even if the fuse F
1
were blown. As a result, the terminal OUT would provide an erroneous voltage.
Capacitor
130
is intended to avoid such malfunction. During power up, capacitor
130
keeps the input of inverter
120
.
3
low sufficiently long to allow the inverter to turn on transistor
110
and discharge the terminal OUT to ground if the fuse is blown. Then the ground voltage on terminal OUT propagates through the three inverters to keep transistor
110
on.
It is desirable to provide alternative programmable latches.
SUMMARY
Some embodiments of the present invention provide simple and reliable programmable latches. Some programmable latches are reliable because they do not depend on delays such as delays provided by capacitor
130
. Dependence on delays is undesirable because delay-dependent circuits may not operate properly if VDD rises slowly. Some latches are simple because they omit capacitor
130
and include only one CMOS inverter.
High reliability is achieved in some embodiments by a diode that keeps a voltage on a latch output terminal within a predetermined range of values before power is supplied to the latch. In some embodiments, the diode's anode is connected to terminal OUT, and the cathode is connected to an external power supply pin EVCC or to a reference voltage terminal. When power is off, the EVCC pin or the reference voltage terminal is at ground, and therefore the voltage on the terminal OUT is not higher than one diode threshold voltage relative to ground (0.65V in some embodiments.) The maximum voltage of 0.65V on terminal OUT allows the latch to be powered up correctly even if fuse F
1
is blown.
In some embodiments, the diode's cathode is connected to a reference voltage which is used also in other parts of the integrated circuit. The reference voltage is generated by a reference voltage generator which includes one or more pull-down resistors connected to the reference voltage terminal and to the ground terminal. When the power is off, these resistors discharge the reference voltage terminal to ground. Hence, the OUT voltage is not higher than one diode threshold relative to ground when the power is off.
Prior art latch of
FIG. 1
has an advantage that a latch initialization does not require a latch initialization signal from outside the latch. The state of the latch is completely determined by the state of fuse F
1
and the voltages on the VDD and ground terminals. This advantage is preserved in some embodiments of the present invention. This advantageously distinguishes such embodiments of the invention from the latch described in U.S. Pat. No. 5,566,107 issued Oct. 15, 1996 to Gilliam in describing a circuit that needs an external “activate” signal for initialization.
Some embodiments do not include a capacitor to generate a delay.
In some embodiments, only one inverter having a pull-up device and one pull-down device is provided between the output terminal OUT and the gate of transistor
110
.
Some embodiments with only one CMOS inverter and no capacitor operate successfully even without a diode because in such embodiments the voltage on the terminal OUT is at the ground level before the power is turned on. The voltage could drift away from the ground level during fuse programming if, for example, the fuse is programmed electrically. (Of note, some embodiments use laser programmable fuses rather than electrically programmable fuses.) However, even if the voltage on terminal OUT becomes high when the fuse is being programmed, the power is turned off after programming, and the voltage on the terminal OUT is allowed to return to ground before the power is turned on again.
Further, in some embodiments, even if the voltage on the terminal OUT is at a high value immediately before the power is turned on, the latch operates properly due to the selection of the trip voltage of the inverter and/or the threshold voltage of transistor
110
.
Other features and advantages of the invention are described below. The invention is defined by the appended claims.


REFERENCES:
patent: 4387503 (1983-06-01), Aswell et al.
patent: 4404635 (1983-09-01), Flaker
patent: 4532402 (1985-07-01), Overbeck
patent: 4532607 (1985-07-01), Uchida
patent: 4546455 (1985-10-01), Iwahashi et al.
patent: 4571704 (1986-02-01), Bohac, Jr.
patent: 4614881 (1986-09-01), Yoshida et al.
patent: 4617651 (1986-10-01), Ip et al.
patent: 4725979 (1988-02-01), Hoberman
patent: 4771285 (1988-09-01), Agrawal et al.
patent: 4779229 (1988-10-01), Agrawal
patent: 4837520 (1989-06-01), Golke et al.
patent: 4852044 (1989-07-01), Turner et al.
patent: 4943804 (1990-07-01), Lee et al.
patent: 5066998 (1991-11-01), Fischer et al.
patent: 5086331 (1992-02-01), Hartgring et al.
patent: 5134585 (1992-07-01), Murakami et al.
patent: 5185291 (1993-02-01), Fischer et al.
patent: 5258953 (1993-11-01), Tsujimoto
patent: 5440246 (1995-08-01), Murray et al.
patent: 5455937 (1995-10-01), Berman et al.
patent: 5459684 (1995-10-01), Nakamura et al.
patent: 5497355 (1996-03-01), Mills et al.
patent: 5506638 (1996-04-01), Cowles et al.
patent: 5526320 (1996-06-01), Zager et al.
patent: 5544124 (1996-08-01), Zager et al.
patent: 5566107 (1996-10-01), Gilliam
patent: 5640364 (1997-06-01), Merritt et al.
patent: 5696455 (1997-12-01), Madurawe
patent: 5710741 (1998-01-01), McLaury
patent: 5793688 (1998-08-01), McLaury
patent: 5812489 (1998-09-01), Matsui
patent: 5870342 (1999-02-01), Fukuda
patent: 5889414 (1999-03-01), Li et al.
patent: 5892712 (1999-04-01), Hirose et al.
patent: 5898621 (1999-04-01), Takahashi et al.
patent: 5952833 (1999-09-01), Morgan
patent: 6084803 (2000-07-01), Sredanovic et al.
patent: 288 689 (1983-10-01), None
B. Prince, “High Performance Memories” New Architecture DRAMs and SRAMs Evolution and Function,1996, pp. 135-227.
B. Prince, “Semiconductor Memories” A Handbook of Design, Manufacture and Application, Second Edition, (1991), pp. 762-764.
“Synchronous Graphics RAM” Micron Technology, Inc. of Boise Idaho, 1998, pp. 1-45.

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