Programmable IO architecture

Details Programmable IO architecture Programmable IO architecture

2011-07-05

2011-07-05

Crawford, Jason M (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S087000, C327S109000, C327S112000, C327S170000

Reexamination Certificate

active

07973563

ABSTRACT:
A buffer device coupled to at least one input/output port of an integrated circuit has a plurality of control inputs configured to receive configuration programming information. The at least one input/output circuit is capable of: (a) being configured in a directional sense of communication by the configuration programming information, (b) being configured as an input circuit which can be further configured to provide input logic switching level thresholds according to the configuration programming information, and (c) being configured as at least one output circuit which can be further configured to provide an output drive strength according to the configuration programming information.

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Declaration of Greg Richmond, Vice President of Engineering and Chief Technical Officer of SpectraLinear, Inc., under 37 CFR 1.56, Feb. 18, 2010.

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