Programmable interleaving in multiple-bank memories

Details Programmable interleaving in multiple-bank memories Programmable interleaving in multiple-bank memories

2008-07-08

2008-07-08

Sough, Hyung (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S206000, C711S202000

Reexamination Certificate

active

11297859

ABSTRACT:
A method includes receiving a linear address for accessing a multiple-bank memory, determining a first bit location of the linear address based on a first register value, and providing a bank identifier based on a value at the first bit location of the linear address. Another method includes receiving, at a memory controller coupled to a multiple-bank memory, input indicating a mapping of values at identified bit locations of a linear address to corresponding values of a memory address output. The memory address output includes a bank identifier based on a value at one or more of at least three bit locations of the linear address and a value of the input is programmable.

REFERENCES:
patent: 6381668 (2002-04-01), Lunteren
patent: 6877076 (2005-04-01), Cho et al.
patent: 2006/0047886 (2006-03-01), Leaback

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