Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
2001-05-08
2004-10-19
Elamin, A. (Department: 2116)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
C713S400000, C713S401000, C713S600000, C713S001000, C713S002000, C713S100000, C709S200000, C709S202000, C709S228000, C709S233000, C709S245000, C712S011000, C712S016000, C712S220000, C455S073000, C455S130000, C455S448000
Reexamination Certificate
active
06807640
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to digital system design in general, and, more particularly, to a programmable interface controller that is suitable for spanning clock domains.
BACKGROUND OF THE INVENTION
FIG. 1
depicts a block diagram of a digital system in the prior art that spans multiple clock domains. The system comprises data source
101
, communications path
102
, interface controller
103
, communications path
104
, output device
105
, clock generator
107
, and clock generator
108
. In accordance with digital system
100
, data source
101
operates in accordance with a first clock from clock generator
107
and output device
105
operates in accordance with a second clock from clock generator
108
.
When clock generator
107
produces a clock with a different clock rate (i.e., frequency) or a different phase than the clock from clock generator
108
, interface controller
103
comprises circuitry for ensuring the reliable transmission of data from data source
101
to output device
105
and across the clock domain boundary. Typically, interface controller
103
typically ran at a clock rate that was some multiple of the first clock rate or the second clock rate to enable it to synchronize with both the data source
101
and output device
105
. In low power (e.g., battery powered, etc.) applications, this is disadvantageous because the high clock rate of interface controller
103
causes a great deal of power consumption.
Therefore, the need exists for an interface controller that is suitable for spanning clock domains and that can have a lower power consumption than interface controllers in the prior art.
SUMMARY OF THE INVENTION
The present invention provides a technique for transmitting data to an output device without some of the costs and disadvantages associated with techniques for doing so in the prior art. In particular, the first illustrative embodiment provides an interface controller that is suitable for spanning clock domains, and the second illustrative embodiment provides an interface controller that is useful in fully synchronous systems (i.e., systems in which the data source and the output device operate in accordance with a single clock). The interface controller in both the first and second illustrative embodiments can be powered-down when not needed, which is particularly useful in low-power applications. Furthermore, the interface controller in both the first and second illustrative embodiments is programmable by the data source, which is particularly useful in off-loading from the data source to the interface controller some of the computational tasks associated with outputting data.
Both illustrative embodiments provide a data source, which generates data, and an interface controller, which transmits the data to the output device and which assists the data source in preparing the data for output. In a fully synchronous system, both the data source and the interface controller operate in accordance with a single clock. In a system that spans clock domains, the data source operates in accordance with a first clock, and the interface controller operates in accordance with a second clock, which is synchronized with the output device's clock.
In both cases, the interface controller comprises a programmable processor that is programmed by the data source on how to process the data to be output. In accordance with the illustrative embodiments, the data source transmits one or more field identifiers and an indication of an order by which each of the field identifiers is to be uniquely associated with each field in a sequence of fields. This is because the data source will afterwards transmit the data in each of the fields, one after another, to the interface controller without any explicit identification of the fields, and, therefore, the interface controller must have some deterministic mechanism for uniquely associating each received field with a field identifier.
The illustrative embodiments comprise: receiving a plurality of field identifiers and an indication of an order by which each of the plurality of field identifiers is to be uniquely associated with each field in a sequence of fields; receiving a stream of data that comprises the sequence of fields and an indication of the boundary between successive fields in the sequence of fields; and processing each field in the stream of data in accordance with the field identifier uniquely associated with that field.
REFERENCES:
patent: 4549228 (1985-10-01), Dieterich
patent: 5166674 (1992-11-01), Baum et al.
patent: 5247657 (1993-09-01), Myers
patent: 5289580 (1994-02-01), Latif et al.
patent: 5564117 (1996-10-01), Lentz et al.
patent: 5588117 (1996-12-01), Karp et al.
patent: 5745886 (1998-04-01), Rosen
patent: 5758291 (1998-05-01), Grube et al.
patent: 6310884 (2001-10-01), Odenwald, Jr.
patent: 6314500 (2001-11-01), Rose
patent: 6317804 (2001-11-01), Levy et al.
patent: 6493342 (2002-12-01), Breslow et al.
patent: 6519234 (2003-02-01), Werkander
patent: 6581164 (2003-06-01), Felts et al.
patent: 6665810 (2003-12-01), Sakai
patent: 6747997 (2004-06-01), Susnow et al.
patent: 2002/0078252 (2002-06-01), Fields et al.
NEC Electronics, Inc. “1987 Microcomputer Data Book, Microprocessors, Peripherals, and DSP Products,” vol. 2 of 2, Aug., 1986. (In particular, the FIFO buffer on p. 6-167 and the HGDC on p. 6-169.
Intel “MCS-96 User's Manual,” 1984. (In particular, the HSIO Unit on p. 2-1 and associated text on pp. 2-13 through 2-14.
Intel “Back to Basics: High Speed Output for the 8XC196KC/KD,” from Intel Developer's CD ROM, 1997.
DeMont & Breyer LLC
Elamin A.
Intersil America's Inc.
Patel Nitin C.
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