Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
2006-08-01
2006-08-01
Le, Don (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S041000
Reexamination Certificate
active
07084666
ABSTRACT:
A programmable interconnect structure in an integrated circuit comprising: a plurality of wires; and a buffer comprising an input and an output, said buffer receiving a weak signal at the input and providing a buffered signal at the output; and a first programmable multiplexer comprising: a plurality of inputs and an output, wherein the inputs are coupled to said plurality of wires, and the output is coupled to said input of the buffer; and a user configurable configuration circuit comprising a plurality of memory elements, wherein the data stored in the memory elements select one of said plurality of wires to couple to said buffer input; and a second programmable multiplexer comprising: an input and a plurality of outputs, wherein the input is coupled to said output of the buffer and the outputs are coupled to said plurality of wires; and a user configurable configuration circuit comprising a plurality of memory elements, wherein the data stored in the memory elements select said buffer output to couple to one of said plurality of wires; wherein, a signal received by the buffer on any one of the plurality of wires is buffered and transmitted to one or more of the other wires. The area of the structure is significantly reduced by increasing the number of programmable switches, generating a layout efficient wire sharing multiplexing scheme, moving the memory elements to a vertical position and using a single large area output stage in the buffer.
REFERENCES:
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4706216 (1987-11-01), Carter
patent: 4761768 (1988-08-01), Turner et al.
patent: 4783763 (1988-11-01), Bergman
patent: 4870302 (1989-09-01), Freeman
patent: 4873459 (1989-10-01), El Gamal et al.
patent: 5331226 (1994-07-01), Goetting
patent: 5343406 (1994-08-01), Freeman et al.
patent: 5455521 (1995-10-01), Dobbelaere
patent: 5488316 (1996-01-01), Freeman et al.
patent: 5656950 (1997-08-01), Duong et al.
patent: 5739713 (1998-04-01), Sharpe-Geisler
patent: 5835405 (1998-11-01), Tsui et al.
patent: 5844422 (1998-12-01), Trimberger et al.
patent: 5942913 (1999-08-01), Young et al.
patent: 6134173 (2000-10-01), Cliff et al.
patent: 6137308 (2000-10-01), Nayak
patent: 6239613 (2001-05-01), Reddy et al.
patent: 6275065 (2001-08-01), Mendel
patent: 6331789 (2001-12-01), O-Bach
patent: 6448808 (2002-09-01), Young et al.
patent: 6515511 (2003-02-01), Sugibayashi et al.
patent: 6630842 (2003-10-01), Lewis et al.
patent: 6747482 (2004-06-01), Ting
patent: 6781408 (2004-08-01), Langhammer
patent: 6812737 (2004-11-01), Sueyoshi et al.
patent: 6828824 (2004-12-01), Betz et al.
patent: 2002/0186044 (2002-12-01), Agrawal et al.
patent: 2003/0085733 (2003-05-01), Pugh et al.
Seals & Whapshott, “Programmable Logic—PLDs and FPGAs”, 1997, pp. 102-117, McGraw-Hill, USA, no month.
Ashok K. Sharma, “Programmable Logic Handbook—PLDs, CPLDs, & FPGAs”, 1998, pp. 99-171, McGraw-Hill, USA, no month.
V. Betz, J. Rose, A. Marquardt, “Architecture and CAD for Deep-Submicron FPGAs”, Feb. 1999, Kluwer Acadamic Publishers, Boston, no month.
Guy Lemieux, David Lewis, “Design Interconnection Networks for Programmable Logic”, 2004, pp. 123-132, Kluwer Acadamic PUblishers, Boston, no month.
Le Don
Viciciv Technology
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