Programmable interconnect circuit with a phase-locked loop

Details Programmable interconnect circuit with a phase-locked loop Programmable interconnect circuit with a phase-locked loop

2001-12-14

2003-12-09

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C327S159000, C327S156000, C331S025000

Reexamination Certificate

active

06661254

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to programmable interconnect circuits, and more particularly to a programmable interconnect circuit having an architecture suitable for bus switching applications.
DESCRIPTION OF RELATED ART
In-system-programmable interconnect devices permit a user to programmably route signals between pins of the device. For example, Lattice Semiconductor Corp. currently manufactures an ispGDX® family of programmable interconnect devices having a non-volatile E
2
CMOS® in-system-programmable crossbar switch matrix for programmable switching, interconnect, and jumper functions. Each pin of the ispGDX® device is associated with an input/output (I/O) circuit that programmably couples to other I/O circuits through a routing structure denoted as a global routing pool (GRP). The I/O circuits contain registers allowing the input and output signals on the associated pins to be selectively registered.
Referring now to
FIG. 1
, an input/output circuit
10
for an ispGDX® device couples to a 4:1 multiplexer (Mux)
12
that receives signals A, B, C, and D from four different routing structures, GRP_A, GRP_B, GRP_C, and GRP_D, (not illustrated) respectively. Each routing structure corresponds to a given quadrant (a side of the integrated circuit) for the device. Accordingly, GRP_A receives the input signals from I/
0
pins
20
in quadrant A, GRP_B receives the input signals from I/
0
pins
20
in quadrant B, and so on. Input/output circuit
10
receives its input signals from its pin
20
and directs them to the appropriate global routing structure on path
19
. For example, if I/
0
circuit is within quadrant A, path
19
would couple to GRP_A.
Each routing structure is a switch matrix that may receive input signals from selected I/O circuits and programmably route output signals to selected I/O circuits. For clarity, the individual structures are grouped together and jointly designated by a single routing structure
14
. A similar device or circuit is disclosed in U.S. Pat. No. 6,034,541, the contents of which are hereby incorporated by reference in their entirety. In addition, each global routing pool has a switch matrix fused by an in-system-programmable non-volatile E
2
CMOS® memory bank, configured for one-way routability. A given memory cell in the volatile E
2
CMOS® memory bank controls the state of a “fuse point” in the switch matrix. The fuse point may be formed by, e.g., a pass transistor that will programmably connect an input lead of the switch matrix to an output lead of the switch matrix, depending upon the logical state (high or low) of the fuse point's memory cell. I/O pins
20
to the device are arranged in quadrants (the four sides to the chip) such that an individual routing structure receives signals from the I/O circuits
10
in a single quadrant and may distribute these signals to the I/O cells
10
in all four quadrants. Thus, the four input signals A, B, C, and D for each Mux
12
are “quadrant” limited to originate in their respective quadrants. Note that, with respect to routing structure
14
, each I/O circuit
10
is independent and separate from the remaining I/O circuits. Because routing structure
14
distributes signals independently to each I/O circuit
10
, the resulting arrangement may be denoted as “pin-oriented” or “bit-oriented” in that each I/O circuit
10
associates with a single I/O pin
20
.
Similar to the data signals, control signals, such as the set/reset, clock, and clock enable (CE) for an input/output register (not illustrated) located within I/O circuit
10
, the output enable (OE) for an output buffer (not illustrated) located within I/O circuit
10
, as well as the MUX selects for MUX
12
, are also limited to originating in a subset of pins
20
from each quadrant. Moreover, the prior art device had no control logic capability for these control signals such that the control function for each signal was limited to a single pin.
Although this “bit-oriented” architecture allowed a user to programmably interconnect signals through the device, the number of fuses in the resulting global routing pool becomes prohibitive as the pin count increases. However, modern board density continues to increase, demanding an interconnect device having a suitable number of pins to interconnect the signals. In addition, board clock speeds continue to increase, making clock skew problematic and clock distribution increasingly difficult.
Accordingly, there is a need in the art for an improved programmable interconnect device that uses fewer fuses and provides the capability for distributing a clock signal through its routing structure.
SUMMARY
In accordance with one aspect of the invention, a programmable semiconductor device includes a plurality of input/output (I/O) cells, each I/O cell having a register associated with a pin. A routing structure couples to the I/O cells and is configured to receive a signal from each I/O cell's register and programmably route the received signal to any of the remaining I/O cells'registers. A phase-locked loop (PLL) is operable to receive an external clock signal and provide an internal clock signal to the registers in the I/O cells, whereby the registers in the I/O cells may all be synchronously clocked with respect to the external clock signal.


REFERENCES:
patent: 6034541 (2000-03-01), Kopec, Jr. et al.
patent: 6177844 (2001-01-01), Sung et al.
patent: 6218876 (2001-04-01), Sung et al.

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