Programmable interconnect architecture using fewer storage cells

Details Programmable interconnect architecture using fewer storage cells Programmable interconnect architecture using fewer storage cells

1993-04-19

1995-04-11

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Array

34082591, 326 44, H03K 19173, H03K 19094

Patent

active

054061385

ABSTRACT:
A first user re-programmable interconnect architecture is provided wherein N switching elements are connected between selected interconnect conductors. The switching elements are controlled by M active storage elements, where M<N. A group of N switching elements are controlled by a group of M active storage elements, where M<N. The states of the M active storage elements are collectively decoded to identify the one of N switching elements to be turned on. A second user re-programmable interconnect architecture is provided wherein a group of N switching elements are connected between selected interconnect conductors and are partially selected by decoding the states of m.sub.1 active storage elements. The group of N switching elements are also partially selected by decoding the states of m.sub.2 active storage elements. The decoding is arranged such that the states of m.sub.1 and m.sub.2 active storage elements each are decoded to provide a partial address to identify one of the N switching elements to be turned to its "on" state. The sum of m.sub.1 and m.sub.2 is less than N. Decoder lines in non-parallel relationship with the interconnect conductors provide increased routability. Partial depopulation of the matrices containing the switching elements provides added routability.

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