Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
2000-03-02
2001-10-09
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S037000, C326S041000
Reexamination Certificate
active
06300792
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to increasing the efficiency of utilization of input, output, and/or input/output pins on integrated circuits such as programmable logic devices. (For ease of reference, all pins—whether input, output, or input/output—are generally referred to generically herein as input/output or I/O pins. Also for ease of reference, multiplexing and demultiplexing of signals are both sometimes referred to simply as multiplexing.)
It has been proposed to increase data throughput through I/O pins of integrated circuits by time-division multiplexing data flowing through those pins. Sample et al. U.S. patent 6,020,760, for example, shows integrated circuits such as programmable logic devices in which I/O pins can optionally transmit and/or receive different data signal values in association with each half of each cycle of the circuit's basic clock signal. This is twice the normal data rate, in which only one data signal value is transmitted or received during each full clock signal cycle. Accordingly, the Sample et al. reference shows increased pin utilization efficiency, which can help to alleviate possible shortages of pins in dense integrated circuits. (The Sample et al. reference is hereby incorporated by reference herein in its entirety.)
Circuitry of the type shown in the above-mentioned Sample et al. reference may add signal switching (multiplexing) to circuit paths that may sometimes be needed for speed-critical signals. Such additional multiplexing tends to add delay and may therefore be undesirable for possibly speed-critical circuit paths.
In view of the foregoing, it is an object of this invention to provide improved circuitry for optionally multiplexing signals on I/O pins of integrated circuits.
It is a more particular object of this invention to provide circuitry which allows two data signals to be optionally multiplexed onto a single I/O pin without introducing additional delay into the I/O pin path, especially when the optional multiplexing is not in use and only a single signal is to pass through the I/O pin.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable output circuitry having at least two data registers (flip-flops) that can operate either separately (when only a single output signal is to be applied to an associated I/O pin) or together (when two output signals are to be multiplexed onto the associated I/O pin). The two registers are preferably a data output register and a tri-state buffer control signal register. When only a single output signal is to be applied to the I/O pin, the data output register may be used to register that output signal and the tri-state buffer control signal register may be used to register a signal for controlling a tri-state buffer that selectively drives the output signal onto the I/O pin. When two data signals are to be multiplexed onto the I/O pin, one of the data signals is registered by the data output register and the other data signal is registered by the tri-state buffer control signal register and fed out through part of the data output register at the appropriate time. Because the second data signal is fed out through part of the data output register, no additional signal switching or multiplexing is needed downstream from the data output register and no additional signal propagation delay is introduced into what may otherwise be needed for speed-critical output signaling.
For demultiplexing two input signals received via a single I/O pin, a latch (e.g., a level-sensitive latch) is added to input circuitry associated with the I/O pin. The level-sensitive latch is connected in parallel with one of at least two other registers (e.g., a data input register) in the input circuitry, and in series with the other of those two registers (e.g., the above-mentioned tri-state driver control signal register). One of the two multiplexed input signals is sampled and registered by the data input register during one of two halves of each clock signal cycle. The other of the two input signals is detected by the latch during the other of the two halves of each clock signal cycle, and then registered by the tri-state driver control signal register. The two input signals can then be fed out from the two registers in parallel.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 5561773 (1996-10-01), Kalish et al.
patent: 5944813 (1999-08-01), Trimberger
patent: 6020760 (2000-02-01), Sample et al.
J. Babb et al.,“Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators,” Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines '93 (FCCM '93), Apr. 1993.
“Virtual Wires,” webmaster @cag.lcs.mit.edu$Date: 1995/02/03, Feb. 3, 1995.
“System Design with New XC4000X I/O Features,” Application Note XAPP 056, Nov. 6, 1997 (Version 1.2), Xilinx, Inc., pp. 1-8.
“XC4000E and XC4000X Series Field Programmable Gate Arrays,” Product Specification, May 14, 1999 (Version 1.6), Xilinx, Inc., pp. 6-5 through 6-72.
“XC4000XLA/XV Field Programmable Gate Arrays,” Product Specification, DS015 (v1.3), Oct. 18, 1999, Xilinx, Inc., pp. 6-157 through 6-170.
Altera Corporation
Fish & Neave
Jackson Robert R.
Tokar Michael
Tran Anh Q.
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