Electronic digital logic circuitry – Interface – Supply voltage level shifting
Patent
1998-03-17
2000-02-22
Santamauro, Jon
Electronic digital logic circuitry
Interface
Supply voltage level shifting
326 50, 326 58, 326 83, H03K 190185
Patent
active
060284501
ABSTRACT:
A programmable input/output (I/O) circuit for transmitting output signals on or receiving input signals from an I/O terminal, the I/O circuit including a pull-up transistor, a gate bias control circuit and a well bias control circuit, all being connected between Vcc and the I/O terminal. The gate bias control circuit connects the gate of the pull-up transistor to the I/O terminal and the well bias control circuit connects the bulk terminal of the pull-up transistor to the I/O terminal when the I/O circuit is in a 5V tolerant input mode. The gate bias control circuit connects the gate of the pull-up transistor to the system voltage source and the well bias control circuit connects the bulk terminal of the pull-up transistor to Vcc when the I/O circuit is in a PCI compliant input mode. In an output mode, the gate bias control circuit and well bias control circuit allow the pull-up transistor to pull up the I/O terminal to Vcc in response to a pull-up data signal.
REFERENCES:
patent: 5144165 (1992-09-01), Dhong et al.
patent: 5396128 (1995-03-01), Dunning et al.
patent: 5764077 (1998-06-01), Andresen et al.
patent: 5933025 (1999-08-01), Nance et al.
Bever Patrick T.
Harms Jeanette S.
Santamauro Jon
Xilinx , Inc.
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