Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1999-01-27
2001-04-17
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S062000
Reexamination Certificate
active
06218858
ABSTRACT:
FIELD OF USE
The invention is useful in the field of FPGA designs, and, more particularly, in FPGAs that are to be used in circuits where input signals may be received from TTL, GTL, GTLP, LVPECL or LVDS circuits or which may have to drive TTL, GTL or GTLP circuits.
FPGAs frequently are used to implement certain functions in other circuits and to provide flexible functionality. However, the number of potential applications for FPGAs is huge so FPGAs will be called upon in various applications to receive input signals from a large variety of different types of circuits having different voltage swing standards between logic 1 and logic 0. Likewise, FPGAs will be called upon in various applications to drive a variety of different types of circuits with output signals which must meet the standards of voltage level for logic 1 and logic 0 of the driven circuit.
Prior art FPGAs have difficulty adapting to use in different applications with circuits driving their input pins with voltage levels which are different than the voltage levels for which the circuitry inside the FPGA was designed for. Likewise, prior art FPGAs have difficulty driving circuitry that require input signals with logic levels which have different voltages than the voltage levels the FPGA is designed to generate. Prior to this invention, only one I/O standard had been offered for FPGAs. That standard was a CMOS I/O which was TTL compatible with slew rate control. This means that the output is CMOS but the logic swings are TTL compatible with some programmability of slew rate control. However, there are other logic families for CMOS and TTL, and new families are being developed. Other families include GTL, GTLP, LVPECL and LVDS. Each of these other families has different requirements for logic 0 and logic 1 voltage levels, voltage reference levels, offset and/or swing. Prior art FPGA CMOS I/O circuits either have difficulty being compatible with these diverse standards or require external conversion circuitry to be compatible.
Thus a need has arisen for an FPGA with a programmable I/O circuit which can accept input signals from many different types of logic families and complying with their native standards and which can drive circuits from different logic families in accordance with their diverse standards.
SUMMARY OF THE INVENTION
The genus of the invention includes any programmable circuitry that can be configured with programming bits to assume any one of the configurations given in
FIGS. 1 through 6
or any other FPGA driver or input circuits already existing or developed in the future to drive signals to external circuits off the FPGA or receive signals into the FPGA from off-chip circuits in new technology families already developed, in the process of development or to be developed in the future. Essentially, the invention is a programmable I/O circuit for an FPGA which, by changing some programming bits, can be transformed into any one of the FPGA driver or input circuits shown in
FIGS. 1-6
or any other currently existing input circuit or driver for an FPGA which currently exists but is not supported by the products of the assignee or which is developed in the future. Essentially, the details of the actual input circuits themselves or drivers themselves on board the FPGA are not important since these circuits are already known or will become known in the future. It is the programmability to transform a programmable input circuit or driver from an input circuit or driver compatible with a first technology family to an input circuit which is compatible with a second technology family or any other logic family that is the essence of what is new. The exact details of how the programmability is achieved are not critical, so long as the FPGA I/O circuit is programmable so as to be compatible with existing or future developed off chip technology families.
A subgenus within this main genus includes programmable slew rate. This is achieved by having multiple parallel transistors either with different channel widths which may be substituted or by having multiple parallel transistors all with the same channel width which may be added in parallel to add additional current sinking or current sourcing capability to alter the slew rate.
REFERENCES:
patent: 5877632 (1999-03-01), Goeting et al.
patent: 5977795 (1999-11-01), Lee
patent: 6005414 (1999-11-01), Reay
patent: 6049227 (2000-04-01), Goetiing et al.
patent: 6052014 (2000-04-01), Maeda
Bobra Yogendra Kumar
Ghia Atul V.
Menon Suresh Manohar
Zaliznyak Arch
Cho James H
Fish, Esq. Ronald C.
Tokar Michael
Xilinx , Inc.
Young Edel M.
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