Programmable I/O structure for FPGAs and the like having...

Details Programmable I/O structure for FPGAs and the like having... Programmable I/O structure for FPGAs and the like having...

2005-09-13

2005-09-13

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S047000

Reexamination Certificate

active

06943583

ABSTRACT:
A programmable device such as a field-programmable gate array (FPGA) has programmable I/O circuitry. In one embodiment, a programmable I/O circuit (PIC) associated with at least first and second pads of the device has an output buffer that is selectively connected to the first and second pads via corresponding first and second transmission gates. The transmission gates enable an outgoing signal from the output buffer to be individually and selectively presented at the pads, while reducing the capacitive loading at each pad when the corresponding transmission gate is open (i.e., when the outgoing signal is not to be presented at that pad).

REFERENCES:
patent: 5821776 (1998-10-01), McGowan
U.S. Appl. No. 10/671,363, filed Sep. 2003, Andrews et al.

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