Programmable I/O interfaces for FPGAs and other PLDs

Details Programmable I/O interfaces for FPGAs and other PLDs Programmable I/O interfaces for FPGAs and other PLDs

2006-03-07

2006-03-07

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C326S040000, C365S233100, C365S189020

Reexamination Certificate

active

07009423

ABSTRACT:
A programmable logic device (PLD), such as a field programmable gate array (FPGA) has a logic core surrounded on one or more sides by an input/output (I/O) interface having one or more programmable I/O buffers (PIBs). At least one PIB can be programmed to perform two or more of (a) a pass-through data input mode, (b) an input register mode; (c) a double data rate (DDR) input mode, (d) one or more demux input modes, (e) one or more DDR demux input modes. In addition or alternatively, at least one PIB can be programmed to perform two or more of (a) a pass-through data output mode, (b) an output register mode, (c) a DDR output mode, (d) one or more mux output modes, and (e) one or more DDR mux output modes. As such, devices of the present invention are flexible enough to support both low-rate and high-rate interface applications, while efficiently using device resources.

REFERENCES:
patent: 6005412 (1999-12-01), Ranjan et al.
patent: 6472904 (2002-10-01), Andrews et al.
patent: 6686769 (2004-02-01), Nguyen et al.
patent: 6791889 (2004-09-01), Peterson
patent: 2004/0155690 (2004-08-01), Andrews et al.
U.S. Appl. No. 10/613,462, Andrews et al., pending.

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