Programmable I/O element circuit for high speed logic devices

Details Programmable I/O element circuit for high speed logic devices Programmable I/O element circuit for high speed logic devices

2005-02-08

2005-02-08

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C326S040000, C326S041000

Reexamination Certificate

active

06853215

ABSTRACT:
A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed 110 modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.

REFERENCES:
patent: 5581199 (1996-12-01), Pierce et al.
patent: 5944813 (1999-08-01), Trimberger
patent: 5960191 (1999-09-01), Sample et al.
patent: 6020760 (2000-02-01), Sample et al.
patent: 6300792 (2001-10-01), Pedersen
patent: 6407576 (2002-06-01), Ngai et al.

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