Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Patent
1997-09-29
2000-06-06
Lintz, Paul R.
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
716 16, 716 8, 714 30, 326 16, 326 47, 371 2232, 371 225, G06F 1127, G06F 1750, G01R 313187
Patent
active
060713143
ABSTRACT:
A mask programmable IC is provided that includes dedicated boundary scan logic in the I/O cells. Valuable core logic resources therefore need not be consumed to implement boundary scan logic. In one embodiment, one boundary scan cell is provided per I/O cell. Another embodiment provides great flexibility in emulating any of several FPGAs in any of several packages. In this embodiment, two boundary scan cells are provided for each I/O pad, each cell alone being capable of providing the boundary scan functions associated with one I/O pad. By selectively choosing which of the boundary scan cells are included in the boundary scan data chain, the order of the boundary scan chain of the emulated FPGA in any of two or more packages can be reproduced. Boundary scan behavior is therefore emulated as well as the programmable logic behavior of the FPGA. In one embodiment, additional programmable interconnect lines traversing each boundary scan cell are provided. Theses interconnect lines can be used to programmably connect the data output of a first cell to the data input of second cell which need not be adjacent to the first.
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Baxter Glenn A.
Buch Kiran B.
Law Edwin S.
Cartier Lois D.
Kik Phallaka
Lintz Paul R.
Xilinx , Inc.
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