Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2005-08-30
2005-08-30
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S027000
Reexamination Certificate
active
06937055
ABSTRACT:
A programmable input/output buffer has a first plurality of pull-down transistors connected between a supply voltage and an electrical system conductor on the integrated circuit and a second plurality of pull-down transistors connected between the electrical conductor and the system reference voltage. Reference circuits generate signals to turn on a first number of said first plurality of pull-up transistors and/or a second number of said second plurality of pull-down transistors to provide an input/output buffer impedance matching the impedance of the external transmission line either sending a signal to the programmable input/output buffer or receiving a signal from the programmable input/output buffer.
REFERENCES:
patent: 4719369 (1988-01-01), Asano et al.
patent: 5602494 (1997-02-01), Sundstrom
patent: 6366129 (2002-04-01), Douglas et al.
patent: 6642740 (2003-11-01), Kim et al.
patent: 06163630 (1994-06-01), None
Chen Chao-Wu
Massoumi Ali
Roy Richard Stephen
Cho James H.
MacPherson Alan H.
MacPherson Kwok & Chen & Heid LLP
Mosaic Systems, Inc.
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