Programmable high speed quiet I/O cell

Details Programmable high speed quiet I/O cell Programmable high speed quiet I/O cell

1998-03-30

2001-08-28

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S083000, C326S086000, C326S026000, C326S027000, C326S017000, C326S121000

Reexamination Certificate

active

06281706

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to interface circuits. In particular, the present invention relates to designing low noise programmable output buffers in interface circuits.
2. Discussion of the Related Art
FIG. 1
illustrates a typical communication system
100
, which includes a device
110
communicating with a second device
120
over a signal path
130
. Device
110
drives onto signal path
130
a data signal, which is received into device
120
by an input buffer
122
. Typically, the propagation delay on signal path
130
depends on the drive strength of output buffer
112
, the length of signal path
130
, and the load on signal path
130
resulting from devices coupled to signal path
130
, such as device
120
. Typically, increasing the drive strength of output buffer
112
decreases the propagation delay on signal path
130
. This technique is used frequently in the prior art (see, e.g., U.S. Pat. No. 4,779,013 to Tanaka).
In many situations, however, output buffer
112
is not specifically designed for use with device
110
. Thus, a mismatch can seriously affect the performance of system
100
. For instance, if output buffer
112
has a high drive strength but signal path
130
is only lightly loaded, noise can be introduced into device
120
through input buffer
122
.
FIG. 2
provides an example of a waveform
200
resulting from a overly strong output buffer driving a digital signal onto a lightly loaded signal path. Portion
215
of the waveform
200
represents, in a rising edge transition, the overshoot and brief oscillation (“ringing”) resulting from this mismatch. Similar ringing characteristics are exhibited in a falling edge transition in portion
225
of waveform
200
. The rapid switching of currents in buffer
112
can also lead to ground bounce and high frequency noises and high power dissipation, all of which are undesirable.
SUMMARY OF THE INVENTION
The present invention provides a multistage output buffer with a stepwise variable output drive strength that is user-programmable to match the load presented in an application and consumes less power and produces less noise than prior art buffers.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.


REFERENCES:
patent: 4779013 (1988-10-01), Tanaka
patent: 4825101 (1989-04-01), Walters, Jr.
patent: 5315172 (1994-05-01), Reddy
patent: 5614842 (1997-03-01), Doke et al.
patent: 5617043 (1997-04-01), Han et al.
patent: 5889707 (1999-03-01), Yang

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