Programmable graphics memory apparatus

Details Programmable graphics memory apparatus Programmable graphics memory apparatus

1999-01-29

2002-04-23

Tung, Kee M. (Department: 2671)

Computer graphics processing and selective visual display system

Computer graphics display memory system

Shared memory

C345S543000, C345S531000, C345S556000

Reexamination Certificate

active

06377268

ABSTRACT:

BACKGROUND
The invention relates generally to computer system memory architectures and, more particularly, to a programmable memory architecture that incorporates graphic buffer storage within system memory.
Referring to
FIG. 1
, conventional computer system
100
providing graphics capability may include central processing unit (CPU)
102
, bridge circuit
104
, and bridge circuit
106
. Bridge circuit
104
provides host interface (HI)
108
, system bus interface (SBI)
110
, graphics port (GP)
112
, and memory interface (MI)
114
. Bridge circuit
106
couples system bus
116
to secondary bus
118
.
Graphics controller (GK)
120
uses graphics memory (G-MEMORY)
122
to control the operation of graphics device
124
. For example, graphics controller
120
may use graphics memory
122
to store data needed to render a three-dimensional (3D) image on graphics device
124
. Graphics memory
122
is often dual port random access memory and is typically incorporated within, or as part of, graphics controller
120
.
System memory (SYS-MEMORY)
126
, in contrast to graphics memory
122
, is typically standard dynamic random access memory (DRAM). System memory
126
may be used by CPU
102
during the execution of computer programs (user application programs and system software, for example).
In some computer systems, graphics port
112
and graphics controller
120
conform to the accelerated graphics port (AGP) specification. (See the “Accelerated Graphics Port Interface Specification,” Revision 2.0, May 1998.) In such systems, graphics controller
120
may use a portion of system memory
126
(hereinafter, AGP memory) to store an image's texture information. For example, a fully compliant AGP controller may access system memory
126
directly to obtain an image's texture information.
Notwithstanding AGP memory, computer system
100
generally does not allow graphics controller
120
to use system memory
126
. Nor does computer system
100
generally allow graphics memory
122
to be used for general system needs. Further, system
100
has a relatively high pin count because separate memories are used for system memory
126
and graphics memory
122
. The high pin count, in turn, may make it more difficult to economically manufacture computer system
100
. In addition, the use of separate graphics controller and memory controllers may also result in the duplication of bus interfaces, memory control and so forth. Thus, it would be beneficial to provide a mechanism by which system memory may be effectively used as graphics memory.
SUMMARY
In one embodiment, the invention provides a program storage device having instructions stored thereon for causing a programmable control device to establish a plurality of graphic buffers in a computer system having a banked system memory architecture. The instructions include instructions to obtain a first indication representing a performance characteristic of the computer system, obtain a second indication representing a size of the system memory, select a plurality of graphic buffer designations based on the first and second indications, and establish one graphic buffer for each of the selected graphic buffer designations in system memory, where at least two of the plurality of graphic buffers are located in different banks of the system memory.
In another embodiment, the invention provides a system comprising a graphics controller, a system memory having a plurality of memory banks, and a plurality of graphic buffers accessible by the graphics controller allocated in system memory, where at least two of the plurality of graphic buffers are located in different memory banks.


REFERENCES:
patent: 5450542 (1995-09-01), Lehman et al.
patent: 5659715 (1997-08-01), Wu et al.
patent: 5668992 (1997-09-01), Hammer et al.
patent: 5748968 (1998-05-01), Nally et al.
patent: 5895481 (1999-04-01), Yap
patent: 6104417 (2000-08-01), Nielsen

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