Programmable gate array

Details Programmable gate array Programmable gate array

1999-10-18

2001-11-06

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S035000, C326S037000

Reexamination Certificate

active

06313660

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of electronics, and in particular to the use of programmable gate arrays for implementing asynchronous threshold gates for use in NULL Convention Logic circuits.
BACKGROUND
Previous logic systems, such as boolean logic systems, have employed clocking signals to regulate the sequential processing of binary logic signals. Typically, a logic circuit will respond to multiple inputs to generate an output. As input logic signals propagate through the circuit, the circuit output is unreliable for a period of time corresponding to worst case propagation delays through the individual logic gates. Typically, the output signal is sampled at a time when the output is stable, often by latching the output into a register. The sampling time is set according to an independent clock signal, i.e., one that is not derived from the states of the logic gates themselves.
Asynchronous circuits have been proposed that are intended to operate without an independent clock. One asynchronous logic paradigm is disclosed in U.S. Pat. No. 5,305,463 (“NULL Convention Logic”), which is incorporated herein by reference in its entirety. This paradigm uses logic gates referred to as threshold gates. Within this class, circuits are made with gates having varying numbers of inputs, and varying threshold values.
It is desirable to have a complete family of gates available for rapid prototyping and testing of multi-gate asynchronous circuits. Fabrication of custom integrated circuits is a method for producing a complete family of gates, however, custom fabrication involves turn-around time and cost. A faster and less costly approach to implementing a wide variety of threshold gates is desirable.
SUMMARY
The present invention provides a novel and efficient structure that can be used to implement NULL Convention Logic (NCL) using specifically designed programmable gate arrays. In general, gate arrays may be either field-programmable gate arrays (FPGAs) or mask-programmable gate arrays (MPGAs). In the former case, the circuits are programmed using electrical signals after the fabrication cycle has been completed. In the latter case, the circuits are programmed when the fabrication cycle has only been partially completed by completing the last set of processing steps using customized masks.
FPGAS, such as the Xilinx 4000-series chip, provide the capability for rapid prototyping of hardware systems. However, because of the relatively large nonrecurring engineering costs associated with fabrication, MPGAs are contemplated for high-volume applications after the design has already been fully debugged. The array architecture of the present invention may be used in both FPGA and MPGA implementations. These architectures can be used to implement a wide variety of NULL Convention threshold gates and larger circuits made from such gates. Thus, with the architecture of the present invention, a multi-gate design can be rapidly prototyped, and then easily migrated to the MPGA implementation for high-volume applications.


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