Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1999-06-04
2001-02-13
Nguyen, Viet Q. (Department: 2818)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C708S703000, C708S710000, C708S711000, C708S230000, C708S232000, C708S518000, C708S514000, C708S524000, C708S525000, C708S552000, C708S707000, C326S038000, C326S041000
Reexamination Certificate
active
06188240
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a programmable function block, which is a logic building unit in a logic device that can implement a various functions depending on user programs.
In recent years, the logic devices such as programmable logic devices (PLDs), field programmable gate arrays (FPGAs) or the like have been developing rapidly. By improving of integration density and speed, use of the logic devices has been elaborated not only to emulation on designing of application specific integrated circuits (ASICs) and replacing of simple peripheral circuits, but also to a reconfigurable computer which is able to change hardware configuration in accordance with applications.
In order to implement a wide variety of logic functions, combined multiplexer circuits or look-up tables (LUT) are used in the programmable function blocks of the conventional PLDs or FPGAs. As a result, the PLDs or FPGAs is disadvantageous in that performance diminishes in arithmetic operations, which are frequently used in the computer.
On the other hand, an arithmetic and logic unit (ALU) comprising a full adder as a main component, that is used in general-purpose processors up to now, is superior in performance of arithmetic operation. However, the ALU is not suitable to use as the programmable function block for PLDs or FPGAS. This is because the ALU has a poor function to use as a logic circuit.
In order to overcome the above-mentioned problems, another programmable function block is proposed in the manner which will later be described in conjunction with
FIG. 1
(U.S. patent application Ser. No. 09/169,948). The prior art programmable function block acquires high functionality by adding a pre-logic circuit having a rich logic function to a full adder.
However, two problems still remain in the prior art programmable function block. A first problem is a large delay. A second problem is a large occupied area.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a programmable function block which has various logic functions and performance of high-speed operation.
It is another object of this invention to provide a programmable function block of the type described, which has a small occupied area.
Other objects of this invention will become clear as the description proceeds.
According to an aspect of this invention, a programmable function block comprises a core logic circuit having a first argument input group consisting of first through fourth argument input terminals, a second argument input group consisting of first through fourth argument input terminals, first through third configuration input terminals, a core logic carry output terminal for outputting a core logic carry output signal, a core logic carry generation output terminal for outputting a core logic carry generation output signal, a core logic carry propagation output terminal for outputting a core logic carry propagation output signal, a ripple-core logic carry input terminal for inputting a ripple-core logic carry input terminal, and a sum output terminal for outputting a summed output signal. Connected to interconnection wires and the first and the second argument input groups, an input block includes eighth input selection units for selecting, as eight input selected signals, eight ones of signals on the interconnection wires, a fixed logic value of “1”, and a fixed logic value of “0” The input selection units supplies the eight input selected signals to the first through the fourth argument input terminals of the first and the second argument input groups. Connected to the first through the third configuration input terminals, respectively, first through third memory circuits stores, as first through third stored logic values, a logic value of one bit. The first through the third memory circuits supplies the first through the third stored logic values to the first through the third configuration input terminals, respectively. A carry logic circuit has a ripple carry input terminal for inputting a ripple carry input signal from a ripple carry propagation path, a ripple carry output terminal for outputting a ripple carry output signal to the ripple carry propagation path, a ripple-core logic carry output terminal for supplying the ripple-core logic carry input terminal with a ripple-core logic carry output signal as the ripple-core logic carry input signal, a core logic carry generation input terminal for inputting the core logic carry generation output signal as a core logic carry generation input signal from the core logic carry output terminal, and a core logic carry propagation input terminal for inputting the core logic carry propagation output signal as a core logic carry propagation input signal from the core logic carry propagation output terminal.
In the above-mentioned programmable function block, the core logic circuit uses one of first through fourth aspects which will presently be described.
According to a first aspect of this invention, the core logic circuit comprises a first two-input one-output multiplexer (
10
.
0
) having a first input terminal connected to the first argument input terminal of the first argument input group, a second input terminal connected to the second argument input terminal of the first argument input group, and a control input terminal connected to the third argument input terminal of the first argument input group. The first two-input one-output multiplexer produces, as a first selected output signal, an input signal supplied to the first input terminal thereof when the control input terminal thereof is supplied with a control signal having a logic value of “0”. The first two-input one-output multiplexer produces, as the first selected output signal, an input signal supplied to the second input terminal thereof when the control input terminal thereof is supplied with the control signal having a logic value of “1”. A second two-input one-output multiplexer has a first input terminal connected to the first argument input terminal of the second argument input group, a second input terminal connected to the second argument input terminal of the second argument input group, and a control input terminal connected to the third argument input terminal of the second argument input group. The second two-input one-output multiplexer produces, as a second selected output signal, an input signal supplied to the first input terminal thereof when the control input terminal thereof is supplied with a control signal having a logic value of “0”. The second two-input one-output multiplexer produces, as the second selected output signal, an input signal supplied to the second input terminal thereof when the control input terminal thereof is supplied with the control signal having a logic value of “1”. A third two-input one-output multiplexer has first input terminal connected to the fourth argument input terminal of the second argument input group, a second input terminal connected to the ripple-core logic carry input terminal, and a control input terminal connected to the first configuration input terminal. The third two-input one- output multiplexer produces, as a third selected output signal, an input signal supplied to the first input terminal thereof when the control input terminal thereof is supplied with a control signal having a logic value of “0”. The third two-input one-output multiplexer produces, as the third selected output signal, an input signal supplied to the second input terminal thereof when the control input terminal thereof is supplied with the control signal having a logic value of “1”. A first exclusive OR circuit has a first input terminal connected to the fourth argument input terminal of the first argument input group and a second input terminal connected to an output terminal of the first two-input one-output multiplexer. The first exclusive OR circuit exclusively ORs an input signal supplied to the first input terminal thereof and the first selected output signal supplied to the second input terminal thereof to produce a first exclusivel
NEC Corporation
Nguyen Viet Q.
Sughrue Mion Zinn Macpeak & Seas, PLLC
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