Programmable frequency detector for use with a phase-locked...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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C327S147000, C327S156000, C455S260000

Reexamination Certificate

active

10714037

ABSTRACT:
A frequency detector for use with a PLL utilizes a counter and a preset value to produce frequency information related to a VCO signal. The frequency information is used to control the frequency of the VCO signal and to determine whether the VCO signal should be controlled by the frequency detector or a phase detector. Using the counter and preset value involves establishing a preset value that is used to obtain the desired frequency information. The preset value is set such that the counter is at one-half full-scale at the end of a known time period when the VCO signal is oscillating at a target frequency. When the preset value is set to such a value, the most significant bit of the counter after the known time period indicates whether the frequency of the VCO signal is above or below the target frequency.

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patent: 6329853 (2001-12-01), Iinuma
patent: 6392495 (2002-05-01), Larsson
patent: 2002/0018038 (2002-02-01), Onishi et al.
patent: 2003/0118380 (2003-06-01), Koide
patent: 2005/0057289 (2005-03-01), Pham
B. Wu, R. Walker, “PLL Design in Hp's Gigabit Ethernet Transceiver,” 1997 HP Design Technology Conference Proceedings, pp. 367-375.

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