Programmable feedback delay phase-locked loop for high-speed...

Details Programmable feedback delay phase-locked loop for high-speed... Programmable feedback delay phase-locked loop for high-speed...

2007-04-17

2007-04-17

Kim, Kevin (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S149000, C327S158000

Reexamination Certificate

active

09977045

ABSTRACT:
A phase-locked loop (PLL), a method of programmably adjusting a phase of a reference clock signal and a synchronous sequential logic circuit incorporating the PLL or the method. In one embodiment, the PLL includes: (1) a digital feedback delay line having a plurality of taps and (2) tap selection logic, coupled to the digital feedback delay line, for activating one of the plurality of taps and thereby insert a corresponding delay into the PLL.

REFERENCES:
patent: 5815016 (1998-09-01), Erickson
patent: 5859550 (1999-01-01), Brandt
patent: 5966388 (1999-10-01), Wright et al.
patent: 6025745 (2000-02-01), Lee et al.
patent: 6028462 (2000-02-01), Kyles
patent: 6075398 (2000-06-01), Furman
patent: 6268753 (2001-07-01), Sandusky
patent: 6377101 (2002-04-01), Eto et al.
patent: 6587811 (2003-07-01), Schleifer et al.
patent: 2001/0036160 (2001-11-01), Curran et al.

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