Programmable element latch circuit

Details Programmable element latch circuit Programmable element latch circuit

2000-08-18

2003-04-22

Smith, Matthew (Department: 2183)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C365S230030

Reexamination Certificate

active

06553556

ABSTRACT:

BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates generally to a device and method for testing semiconductor electrical devices. In particular, the present invention relates to simulating a programmable state of a device when the device has already been programmed to another programmable state.
II. Description of the Related Art
In order to ensure proper operation, semiconductor devices are typically tested before being packaged into a chip. A series of probes on a test station electrically contact pads on each die to access the semiconductor devices on the die. For example, in a semiconductor memory device, the probes contact address pads and data input/output pads to access selected memory cells in the memory device. Typical dynamic random access memory (“DRAM”) devices include one or more arrays of memory cells arranged in rows and columns. Each array of memory cells includes word or row lines that select memory cells along a selected row, and bit or column lines (or pairs of lines) that select individual memory cells along a row to read data from, or write data to, the cells in the selected row.
In a test procedure, predetermined data or voltage values are typically written to selected row and column addresses that correspond to certain memory cells, and then the voltage values are read from those memory cells to determine if the read data matches the data written to those addresses. If the read data does not match the written data, then the memory cells at the selected addresses likely contain defects and the semiconductor device fails the test.
Many semiconductor devices, particularly memory devices, include redundant circuitry on the semiconductor device that can be employed to compensate for certain detected failures. As a result, by enabling such redundant circuitry, the device need not be discarded even if it fails a particular test. For example, memory devices typically employ redundant rows and columns of memory cells so that if a memory cell in a column or row of the primary memory array is defective, then an entire row or column or partial row or column of redundant memory cells can be substituted therefor, respectively.
Substitution of one of the redundant rows or columns is conventionally accomplished by blowing selected antifuses in a bank of antifuse latch devices to select redundant rows or columns to replace defective primary rows or columns. Each bank represents a memory address. If a given primary row or column in the array contains a defective memory cell, antifuses in the bank of antifuses are blown such that the bank of antifuses produces a binary output matching the defective address. An antifuse is a capacitive device that may be blown by applying a relatively high voltage across it which causes the dielectric layer in the antifuse to break down and form a conductive path. A blown antifuse will conduct current while an unblown antifuse will not conduct current. For example, if the defective primary row or column has an 8-bit binary address of 00100100, then the appropriate antifuses in a bank of 8 antifuses are blown to store this address. The individual antifuses are generally contained in antifuse latch devices which generate a digital value or signal indicating whether the antifuse is blown or unblown and may be arranged in groups of 8, each group of 8 defining the address fuses for one antifuse bank.
When an address in the memory device is accessed, a compare circuit compares an incoming address to addresses stored in the antifuse banks to determine whether the incoming address matches an address containing a defective memory cell. If the compare circuit determines such a match, then it outputs a match signal to a row or column decoder. In response, the row or column decoder causes an appropriate redundant row or column to be accessed, and ignores the defective primary row or column in the array.
After antifuses have been programmed to store an address of a defective primary row or column, testing often occurs where it would be beneficial if the antifuse latch device could maintain a state other than that programmed. For example, an antifuse latch device may physically have a blown antifuse, but need to simulate an unblown state to test different configurations of the redundant rows or columns.
Redundant elements are typically tested by assigning a pretest address to each antifuse bank. This pretest address is hard coded so that each memory device has the same redundant pretest address, and the test program is therefore valid for every device. Additional test circuitry is required on the memory device to achieve this hard coding of the pretest addresses. As the number of redundant elements increases, the amount of test circuitry required to define the pretest addresses also increases. For ease of testing, it is desirable to have the ability to test redundant elements using pretest addresses even after the elements have been programmed to repair defective memory elements, e.g. after a repair address has been programmed into the antifuse bank.
Traditionally, in a pretest test mode, the antifuse bank is forced to output a match in response to a pretest address regardless of the state of the antifuse latches. The forced match is accomplished through the use of test circuitry, which bypasses the antifuse latch versus input address compare circuitry, and therefore is not accurate in terms of address to match signal delay. In order to generate the match signal, addresses must be decoded and logically combined with the pretest test mode signal to determine when to force the match. This pretest address decoder increases in size as the number of redundant elements on a memory device increases because more address combinations are required to provide enough unique pretest addresses. Providing sequential pretest addresses require an even larger pretest address decoder since more address terms are required for each bank. For example, in the prior art, it has been sufficient to use just one address term ANDed with the pretest signal to decode a redundant element fuse bank. A
0
high would enable bank
0
, A
1
high would enable bank
1
, A
2
high would enable bank
2
, etc. To avoid enabling multiple fuse banks, only address
0
,
2
,
4
, etc. would be valid using this methodology, and the maximum number of unique fuse bank pretest addresses is limited to the number of address inputs to the device. Current memory devices may require 3 or 4 address terms be ANDed together to generate the required number of pretest addresses. Another drawback of this method is that the tester requires a large memory space for the pretest addresses even though only a few of the addresses are actually valid. Thus, there exits a need for an antifuse latch that can be temporarily programmed for test purposes to a state which is independent of the programmed state and which can ideally be programmed into sequential pretest address states.
SUMMARY OF THE INVENTION
The present invention relates to a device and method for use in memory devices employing redundant rows and/or columns. The present invention provides an antifuse latch device which may perform a redundancy pretest using the real time operational signal path. The circuit of the present invention implements a level translating inverter to control a voltage to the gate of a transistor; the transistor having a source terminal connected to the output of an antifuse. The level translating inverter causes the circuit to simulate an unblown antifuse (or state of other similar programmable elements) by not supplying a voltage sufficient to drive the gate of the transistor receiving a signal from a physically blown antifuse. A blown antifuse can also be simulated by rendering the FA (fuse address) signal high to supply a low signal to the latch, where the physical antifuse is unblown.
Thus, the present invention provides more reliable results for a redundancy pretest, as the speed of signal propagation as well as the functionality of other components in the signal path can be observed during the t

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