Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Patent
1996-07-19
1998-03-10
Santamauro, Jon
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
326 86, H03K 190175
Patent
active
057265836
ABSTRACT:
A dynamic termination circuit is disclosed that has a plurality of parallel termination elements that respond successively to a signal transition and which are selectively enabled and disabled to provide a desired impedance match with a transmission line. Each termination element includes a first dynamic resistive path between a voltage supply line and that termination element's output and a second dynamic resistive path between the termination element output and ground, both resistive paths including field-effect transistors whose control gates are responsive to a signal received from the transmission line via an input to the circuit. For successive response, a series of delay elements are provided between the circuit input and the respective termination circuit elements. For selective enablement, logic gates connected between the termination element inputs and the field-effect transistor control gates have enable inputs receiving user-programmable enable signals for the respective termination elements. In addition to the impedance provided by the main dynamic resistive paths to voltage supply and ground, at least one of the termination elements may have supplemental dynamic resistive paths in parallel with the main paths and responsive to a TRIM bit to allow adjustment of the actual impedance to manufacturing tolerances.
REFERENCES:
patent: 4859877 (1989-08-01), Cooperman et al.
patent: 5164663 (1992-11-01), Alcorn
patent: 5287022 (1994-02-01), Wilsher
patent: 5329190 (1994-07-01), Igarashi et al.
patent: 5343503 (1994-08-01), Goodrich
patent: 5361038 (1994-11-01), Allen et al.
patent: 5444406 (1995-08-01), Horne
patent: 5479123 (1995-12-01), Gist et al.
patent: 5528166 (1996-06-01), Iikbahat
patent: 5530377 (1996-06-01), Walls
Chris Hanke et al., "Low Skew Clock Drivers and their System Design Considerations", Motorola Application Note AN1091, 1990.
Michael Dolle, "A Dynamic Line-Termination Circuit for Multireceiver Nets", IEEE Journal on Solid-State Circuits, vol. 28, No. 12, pp. 1370-1373, Dec. 1993.
Protsik Mark
Santamauro Jon
Schneck Thomas
LandOfFree
Programmable dynamic line-termination circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Programmable dynamic line-termination circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable dynamic line-termination circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-142440