Programmable drive circuit for I/O port

Details Programmable drive circuit for I/O port Programmable drive circuit for I/O port

2002-04-15

2003-09-23

Le, Don (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S057000, C326S087000

Reexamination Certificate

active

06624661

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The invention relates to a drive circuit for I/O (Input/Output) ports. More particularly, the invention utilizes a programmable drive circuit to dynamically select an open-drained or push-pull driving circuit on the I/O port of an IC (Integrated Circuit) to achieve communications with a particular CPU (Central Processing Unit).
2. Related Art
In the prior art, there are two types of normal driver architectures for the I/O port: one being the open-drained driving circuits, such as the GTL (Gunning Transmit Logic) bus standards for the I/O port of the Intel P6 CPU; and the other being the push-pull drivers, such as the S2K bus standards for the I/O port of the AMD K7 CPU.
An open-drained driving circuit is shown in FIG.
1
. The circuit includes a resistor load R and an N MOS (N-channel Metal-oxide Semiconductor) transistor Q
A
, connected between a work voltage V
dd
and the ground in series. The gate end of the NMOS transistor Q
A
is connected to an input signal V
in
. The junction between the resistor load R and the drain end provides an output signal V
o
. When V
in
is at a high level, the transistor Q
A
is conductive and the voltage V
R
at a receiving end decreases down to the ground level so that the transistor Q
A
can extract a larger load current. This current can make the load capacitance C rapidly discharge. When V
in
is at a low level, no current flows through the transistor Q
A
and the resistor load R provides a load current. The receiving end voltage V
R
increases up to the level of V
dd
. This current can rapidly charge the load capacitance C.
A push-pull driving circuit is shown in FIG.
2
. The circuit contains a PMOS transistor Q
B
(this P-channel MOS transistor can be replaced by an NMOS transistor too) and an NMOS transistor Q
C
, both being connected between the work voltage V
dd
and the ground in series. The gate end of the PMOS transistor Q
B
is connected to an input signal V
1
and that of the N-type MOS transistor Q
C
to an input signal V
2
. The junction of the drain ends of the two transistors provides an output signal V
o
. When both V
1
and V
2
are low-level input (V
1
is at a high level for the NMOS transistor Q
B
), Q
B
is conductive but Q
C
is not. A load current flows through the transistor Q
B
, rapidly charging the load capacitance C. Consequently, the receiving end voltage V
R
is pulled up to the level of V
dd
. The transistor Q
B
is thus called a pull-up transistor. When both V
1
and V
2
are high-level input (V
1
is at a low level for the N MOS transistor Q
B
), Q
C
is conductive but Q
B
is not. A load current flows through the transistor Q
C
, rapidly discharging the load capacitance C. Consequently, the receiving end voltage V
R
is pulled down to the ground level. The transistor Q
C
is thus called a pull-down transistor element.
For the driving circuits in the prior art, such as those shown in
FIGS. 1 and 2
, the drive circuit design varies for different bus specifications of the I/O port connected to the CPU. For example, the major function of the chip set of a system motherboard is an interface between the CPU and system memory and an interface between the CPU and the external buses for peripheral devices. However, in the same core logic, the drive circuit for the I/O port of the chip set has to comply with the GTL or S2K bus standards for different I/O bus specifications of the P6 or K7 CPU. Therefore, two different I/O port driving circuits have to be provided. This merely complicates the design and the product is limited in its applications.
Therefore, the invention provides a programmable drive circuit to combine the two driving circuits into the I/O port and to control the logic circuits using a select signal. Thus, the I/O port has a programmable circuit for different bus specifications.
An objective of the invention is to provide a programmable drive circuit applicable to the IC I/O port. Using a logic circuit, the I/O port has a circuit structure of both the open-drained and the push-pull driving circuits. Such a design circumvents the necessity of using separate drivers for different system specifications by combining the two driving circuits into the I/O port of an IC.
SUMMARY OF THE INVENTION
As described before, the prior art has to use different drivers in accordance with different IC I/O port specifications. Thus, there are numerous products, resulting in a waste of resources. The invention provides a select signal in the programmable driver of the IC I/O port. Such a select signal switches between the open-drained and push-pull drivers so that the core logic circuit can easily select an appropriate I/O port driver according to the I/O port bus specification.
In an embodiment of the invention, the I/O driver contains a first transistor group and a second transistor group. The I/O is connected between the work voltage and the ground in series. S select signal triggers either a first logic circuit to control the operation of the first transistor group or a second logic circuit to control the operation of the second transistor group. The first transistor group and the second transistor group on the I/O port can function equivalently as either the open-drained driving or the push-pull driving.


REFERENCES:
patent: 4481432 (1984-11-01), Davies, Jr.
patent: 4697107 (1987-09-01), Haines
patent: 5811997 (1998-09-01), Chengson et al.
patent: 6242943 (2001-06-01), El-Ayat

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