Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1990-04-10
2001-03-13
Treat, William M. (Department: 2783)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C703S014000, C703S015000, C712S036000
Reexamination Certificate
active
06202197
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to programmable circuit devices. More particularly, the present invention relates to an architecture that permits the instantaneous realization of certain classes of systems in integrated circuit or discrete component form.
The task of making a commercial integrated circuit is expensive both in terms of time and money. Typically, a desired circuit is designed in a laboratory and modeled. Specifications for the design are then drawn and an integrated circuit design is made from the desired specifications. An integrated circuit is then fabricated according to known techniques. The cost from design to first fabrication is often in the tens of thousands of dollars, and time frame is usually several months. However, after fabrication, the chip must first be tested for errors in specification or design. Such errors, which are rather common, force the redesign of the chip and require another fabrication procedure. Before the entire process is finished, the cost to the designer will be in the many tens of thousands of dollars, if not hundreds of thousands, and the time from start to finish could very well be over a year.
In light of the above, it is clear that the task of creating an integrated circuit is fraught with many shortcomings. Besides the actual costs of designing a functioning chip, the large delays inherent in the process can impart a financial burden in lost revenues. Moreover, the rigid nature of the design process does not allow for interactive product development. Thus, desirable changes are not easily worked into the design, and because of time and dollar constraints may never be incorporated into the final product. Likewise, where an exact determination of the performance of a component is not obtainable in advance, current integrated circuit design techniques would require a user to breadboard his system and then subsequently size and cost reduce it with integrated circuits. Such a method is slow and expensive and is open to a multitude of problems in translating breadboards into chips.
Even after a chip has been perfected, it has to be produced in volume for production. The “productization” of a chip is the process of understanding the failure mechanisms that can limit yield and correcting for them. Increasing the yield reduces the cost of the chip and increases the security of supply. However, increasingly, application specific integrated circuits have been desired resulting in lower volumes of a greater number of different chips. The “productization” of a lower volume chip introduces another significant cost to the overall process. Moreover, with lower volumes, the designer will often face significant inventory problems, as lead times are usually on the order of a few months, but sales from month to month may be quite uneven.
Despite the many shortcomings of the standard manner of producing integrated circuits (ICs), the use of such ICs is virtually mandatory in the production of all electronic products as they could not be constructed with reasonable size and sold at a marketable price without them. On the other hand, the lead time necessary to produce an IC and the cost involved establish a significant entry barrier.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an architecture for the expeditious and cost-effective production of circuitry.
It is a further object of the invention to provide apparatus of an integrated circuit nature capable of being programmed to perform a multitude of useful functions at the command of a user.
It is yet a further object of the invention to provide a system using a plurality of identical apparatus, or a plurality of apparatus of similar architecture, the system being capable of being arranged to perform any of a multitude of desired complex functions at very high speed.
It is another object of the invention to provide a user-friendly system which can take desired configurations and requirements of a user and provide a parameterized, configured circuit capable of conducting desired functions at very high speed.
It is even another object of the invention to provide an apparatus architecture which permits a designer to design and modify an integrated circuit interactively and in real time.
In accord with the objects of the invention, an apparatus is provided which can either serve as the equivalent of an integrated circuit chip, and/or as a building block for a large system. The apparatus includes numerous functional blocks such as serial and parallel ports, D/A and A/D converters, and linear signal processors (LSPs). The LSPs can be programmed with microcode and/or parameters to perform any of numerous desired functions. If desired, instead of LSPS, the functional blocks can be set functional blocks such as biquad filters which are programmable with parameters only. The functional blocks are connected in any desired manner through a switching matrix located in the core. The core controls the switching matrix (topological data) as well as controlling the flow of parametric data, and where relevant the microcode data, to the functional blocks which sets the parameters (and microcode) of the functional blocks. Topological, parametric and microcode data are first received by the core via a communications bus from an external processor which generates the data, or from an external memory means which stores the data in memory for forwarding to the apparatus upon powering up of the same. The topological data are stored at the core, while the parametric and microcode data are forwarded to the functional blocks via a parametric bus. If desired, topological and/or parametric and microcode data may be burned into the switch matrix and functional blocks as permanent programmed memory, or held as programmable nonvolatile (EPROM) or volatile memory (RAM) associated with the core and functional blocks. Signal data, on the other hand, is typically received and transmitted via the serial and/or parallel ports and via the D/A and A/D converters (functional blocks) of the apparatus. Thus, the signal data is processed extremely quickly by having the parameterized (and programmed in the case of the LSP) functional blocks perform their operations on signal data and by forwarding the results to another functional block via the topologically arranged switching matrix.
Each provided apparatus can be made part of a larger system including several identical or architecturally similar apparatus by providing links between the cores of the apparatus. In this manner, each apparatus is a node of a larger system. To maintain processing speed and simplify interconnections, the links between the cores only carry signal and timing data.
Preferably, the provided apparatus and system are part of a user-friendly custom chip building system. Software is provided to permit a user to specify a desired arrangement of functional blocks and parameters for each block. In fact, preferably, a user could draw a desired filter frequency response, and the system could determine the required filter with its filter transfer function which could accomplish the desired output. The system could then automatically configure the apparatus by generating and providing the necessary topological data as well as the parametric (and microcode) data. The user would then be able to test the functioning of the apparatus in its desired environment. If changes were required either in the format of the chip apparatus (i.e. topological changes) or in the parameters or microcode of the functional blocks, these changes could be made in a real time interactive manner while signal data is flowing. When the desired results are obtained, the master program containing the topologic, parametric, and microcode can be stored. If changes in the matrix switching or in the parameters of the functional blocks are not necessary during the running of the program, the parameters and topology can be burned into the chip.
A better understanding of the invention, and additional advantages and objects of the invention wi
Robinson Jeffrey I.
Rouse Keith
Logic Devices Incorporated
Skjerven Morrill & MacPherson LLP
Treat William M.
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