Programmable delay line using configurable logic block

Details Programmable delay line using configurable logic block Programmable delay line using configurable logic block

2006-05-23

2006-05-23

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S040000, C326S038000, C327S400000, C327S401000

Reexamination Certificate

active

07049845

ABSTRACT:
A configurable logic block (“CLB”) in a programmable logic device (“PLD”), such as a complex programmable logic device (“CPLD”) or a field programmable gate array (“FPGA”), routes a timing signal, such as an external clock signal, through the CLB to provide a selected delay. The timing signal is routed through selected fast or slow pins of look-up tables (“LUTs”) in the CLB. CLBs are widely available in the PLD, allowing many timing signals to be delayed, and can be configured to account for board-specific or component-specific delays.

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