Electronic digital logic circuitry – Multifunctional or programmable
Reexamination Certificate
2010-03-03
2011-11-29
Ismail, Shawki (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
C326S041000, C326S047000, C326S101000
Reexamination Certificate
active
08067959
ABSTRACT:
A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.
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Bakker Gregory W.
Jasinoski Tomek P.
Landry Joel
Plants William C.
Zain Suhail
Actel Corporation
Ismail Shawki
Lewis and Roca LLP
Tran Thienvu
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