Programmable delay element

Details Programmable delay element Programmable delay element

2000-04-26

2001-05-29

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Field-effect transistor

Reexamination Certificate

active

06239616

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the design of electronic circuits and in particular, to the design of programmable delay elements.
2. Background Art
A Field-Programmable Gate Array (FPGA) is a digital integrated circuit capable of being programmed to provide a variety of different logic functions. An FPGA is unique in that it allows reprogramming or configuration to define its functionality by using on-chip fuses, EPROM (UV erasable programmable read-only memory) circuits, EEPROM (electrically erasable programmable read-only memory) circuits, and RAM (random access memory) circuits which programmably create data paths and logic functions within the device that are specific to the user's design.
State of the art FPGAs make use of one or more non-volatile memory cell arrays (e.g. EPROM, EEPROM, Flash EPROM, or Flash EEPROM) so that they can retain their configuration memory during power-down. Typically, these arrays are erasable, thereby allowing the desired functionality of the FPGA to be reprogrammed many times.
FIG. 1
is a block diagram of an FPGA architecture which includes Configurable Logic Blocks (CLBs), Input/Output Blocks (IOBs), and a programmable interconnect network. CLBs are configurable circuits that provide the functional elements for constructing the user's logic. The functionality of a CLB or an IOB can be customized during configuration by programming. For example, each CLB shown in
FIG. 1
may perform any one of a variety of logic functions. The logic functions performed by a particular CLB and its interconnections are defined by data stored in associated configuration memory cells. A typical FPGA has tens of thousands of configuration memory cells.
User-configurable IOBs provide the interface between external package pins and the internal logic of the device. Each IOB controls one package pin and is used to control pad functions, such as signal direction, logic threshold, and slew rate. Since there are input, output, and bi-directional signals to deal with, IOBs are designed to be configurable to handle such signals.
In the majority of FPGA architectures, IOBs are connected to the nearest available pad, which seats a metal (usually gold) wire. (The metal wire is used to electrically connect the pad to a lead or a pin which provides the connection to the outside world.) This connectivity provides a uniformity of signal delays between pads and IOBs. However, some FPGA architectures require a “scrambling” of connections between pads and IOBs in order to satisfy the conflicting pin availability constraints of different package types. For example, routing may require IOBs to connect to remote pads due to pin constraints or a special need to connect an IOB to a certain pin such as a power pin or a control signal pin. This connectivity, illustrated in
FIG. 2
, may result in great disparity of signal path lengths and a corresponding spread of signal delays.
Referring to
FIG. 2
, lines
201
-
205
connect IOBs with the nearest available pad, thus providing the shortest signal delay. For example, line
201
connects IOB
221
to the nearest pad
211
; line
202
connects IOB
222
to the nearest pad
212
; line
203
connects IOB
223
to the nearest pad
213
; line
204
connects IOB
224
to the nearest pad
214
; and line
205
connects IOB
225
to the nearest pad
215
. Lines
206
and
207
, however, connect IOBs
226
and
227
with remote pads
216
and
217
, respectively, thereby introducing longer delays in signal propagation along these routes. Consequently, there are significantly different delays for paths
201
and
206
. Other factors that make the delays unpredictable include, for example, process and batch-to-batch variations. In some cases, to compensate for these disparate delays, a user may have to provide customized timing circuitry to handle different timing delays for each PAD/IOB pair.
Thus, it is not only desirable but necessary to equalize these delays, in order that set-up and hold time specifications for a particular device are met without having to provide extra circuitry. Set-up time refers to the time interval during which a signal must be stable at an input terminal prior to an active transition occurring at another input terminal. Hold time refers to the time interval during which a signal must be stable at an input terminal following an active transition occurring at another input terminal. If either a set-up or hold time specification is violated, I/O operations of an FPGA may not complete successfully.
In the past, delay equalization procedures for FPGAs have included: completion of chip artwork such as the floorplan for IOBs and CLBs, extraction of parasitic resistance and capacitance from the layout, and modeling of the interconnect based on these parasitics. These prior art methods further include simulation of path delays using the interconnect models, classification of different delays into “bins” having predefined delay ranges, and modification of chip artwork to incorporate equalization elements.
Unfortunately, these methods are time consuming and have several sources of potential errors and inaccuracies. For example, extraction of parasitic resistances and capacitances is very much dependent on accurate fabrication process characterization. Modeling of interconnects is often imprecise and worsens at sub-micron geometries. The “binning” process, which is necessary to reduce the number of different delay elements required, results in a further loss of precision.
Finally, the exact physical implementations of the delay elements are unlikely to perform as intended due to circuit layout constraints. For example, H. B. Bakoglu, in his treatise on phase-locked loop technique entitled “Circuits, Interconnections, and Packaging for VLSI,” chapter 8, section 6, Addison-Wesley, 1990, discusses difficulties in eliminating clock skew problems due to on-chip RC delays and geometry.
Additional factors to consider are the effects of fabrication process variations. The resulting fabricated devices are likely to require at least one more design iteration before the delays are correctly implemented. If there are other members in a product family, the aforementioned process must be repeated for each family member. Over the life-span of a product, the whole situation may be further complicated by fabrication process enhancements, and shifts of production to different foundries, which render existing delay equalizations obsolete.
In a typical application, output slew rate control is also necessary in addition to input delay control. Typically, an integrated circuit chip is coupled to multiple MOS chips on a PCB (Printed Circuit Board), and high-current output stages are required to drive multiple chips. However, the long lines and distributed input capacitance and inductance in combination with fast output transition times may result in severe ringing. Suppose, for example, that an FPGA chip is configured as SRAM (Static Random Access Memory). In one read operation, the FPGA chip makes a high-to-low transition in all eight (8) data outputs (assuming an eight bit word length). The eight simultaneous transitions can draw a significant amount of transient current out of a power bus that is driving the eight IOBs. This draw of current can force the ground pin to rise momentarily above ground potential, along with any other outputs that are supposed to stay at the ground potential. This level of ground bounce can cause undesired transient behavior at the outputs or in the internal logic, possibly triggering a malfunction or logic errors. The problem is further exacerbated in systems with sixteen (16) or thirty two (32) bit word lengths.
In the past, various methods were used to minimize such power bus transients. In “Forming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS Output Buffers,” IEEE Custom Integrated Circuits Conference, pp 277-280, May, 1996, T. Gabara et al. discuss several techniques for reducing the ground bounce generation.
However, the prior art methods were

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