Programmable delay control for sense amplifiers in a memory

Details Programmable delay control for sense amplifiers in a memory Programmable delay control for sense amplifiers in a memory

1999-03-01

2000-08-29

Tran, Andrew Q.

Static information storage and retrieval

Read/write circuit

Signals

365194, 36523003, 3652257, 365190, 365207, 365208, G11C 708

Patent

active

06111796&

ABSTRACT:
A memory has sense amplifiers that provide data onto a global data lines that are received by secondary amplifiers. The sense amplifiers and the secondary amplifiers are enabled by clocks that are timed by programmable delay circuits. The programmable delays are programmed by delay selection circuits that provide a continuous output to the programmable delay circuits. There are two delay selection circuits. One is shared by all of the programmable delay circuits that enable the sense amplifiers, and one is shared by all of the programmable delay circuits that enable the secondary amplifiers. The outputs of these two delay selection circuits are chosen to provide the output which programs the programmable delay circuits for optimizing the worst case of the access time of the memory.

REFERENCES:
patent: 5289413 (1994-02-01), Tsuchida et al.
patent: 5321661 (1994-06-01), Iwakiri et al.
patent: 5920510 (1999-07-01), Yukutake et al.
patent: 5978286 (1999-11-01), Chang et al.
patent: 6031775 (2000-02-01), Chang et al.

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